706f06c39a
There are a few tests that depend on some target features **not** being enabled by default, and usually they are correct with the default x86-64 target CPU. However, in downstream builds we have modified the default to fit our distros -- `x86-64-v2` in RHEL 9 and `x86-64-v3` in RHEL 10 -- and the latter especially trips tests that expect not to have AVX. These cases are few enough that we can just set them back explicitly.
62 lines
1.8 KiB
Rust
62 lines
1.8 KiB
Rust
// verify that simd mask reductions do not introduce additional bit shift operations
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//@ revisions: x86 aarch64
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//@ [x86] compile-flags: --target=x86_64-unknown-linux-gnu -C llvm-args=-x86-asm-syntax=intel
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//@ [x86] compile-flags: -C target-cpu=x86-64
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//@ [x86] needs-llvm-components: x86
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//@ [aarch64] compile-flags: --target=aarch64-unknown-linux-gnu
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//@ [aarch64] needs-llvm-components: aarch64
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//@ [aarch64] min-llvm-version: 18.0
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//@ assembly-output: emit-asm
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//@ compile-flags: --crate-type=lib -O
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#![feature(no_core, lang_items, repr_simd, intrinsics)]
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#![no_core]
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#![allow(non_camel_case_types)]
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// Because we don't have core yet.
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#[lang = "sized"]
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pub trait Sized {}
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#[lang = "copy"]
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trait Copy {}
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#[repr(simd)]
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pub struct mask8x16([i8; 16]);
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extern "rust-intrinsic" {
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fn simd_reduce_all<T>(x: T) -> bool;
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fn simd_reduce_any<T>(x: T) -> bool;
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}
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// CHECK-LABEL: mask_reduce_all:
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#[no_mangle]
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pub unsafe extern "C" fn mask_reduce_all(m: mask8x16) -> bool {
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// x86: psllw xmm0, 7
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// x86-NEXT: pmovmskb eax, xmm0
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// x86-NEXT: {{cmp ax, -1|xor eax, 65535}}
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// x86-NEXT: sete al
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//
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// aarch64: shl v0.16b, v0.16b, #7
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// aarch64-NEXT: cmlt v0.16b, v0.16b, #0
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// aarch64-NEXT: uminv b0, v0.16b
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// aarch64-NEXT: fmov [[REG:[a-z0-9]+]], s0
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// aarch64-NEXT: and w0, [[REG]], #0x1
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simd_reduce_all(m)
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}
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// CHECK-LABEL: mask_reduce_any:
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#[no_mangle]
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pub unsafe extern "C" fn mask_reduce_any(m: mask8x16) -> bool {
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// x86: psllw xmm0, 7
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// x86-NEXT: pmovmskb
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// x86-NEXT: test eax, eax
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// x86-NEXT: setne al
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//
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// aarch64: shl v0.16b, v0.16b, #7
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// aarch64-NEXT: cmlt v0.16b, v0.16b, #0
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// aarch64-NEXT: umaxv b0, v0.16b
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// aarch64-NEXT: fmov [[REG:[a-z0-9]+]], s0
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// aarch64-NEXT: and w0, [[REG]], #0x1
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simd_reduce_any(m)
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}
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