rust/library
bors ee86f96ba1 Auto merge of #85828 - scottmcm:raw-eq, r=oli-obk
Stop generating `alloca`s & `memcmp` for simple short array equality

Example:
```rust
pub fn demo(x: [u16; 6], y: [u16; 6]) -> bool { x == y }
```

Before:
```llvm
define zeroext i1 `@_ZN10playground4demo17h48537f7eac23948fE(i96` %0, i96 %1) unnamed_addr #0 {
start:
  %y = alloca [6 x i16], align 8
  %x = alloca [6 x i16], align 8
  %.0..sroa_cast = bitcast [6 x i16]* %x to i96*
  store i96 %0, i96* %.0..sroa_cast, align 8
  %.0..sroa_cast3 = bitcast [6 x i16]* %y to i96*
  store i96 %1, i96* %.0..sroa_cast3, align 8
  %_11.i.i.i = bitcast [6 x i16]* %x to i8*
  %_14.i.i.i = bitcast [6 x i16]* %y to i8*
  %bcmp.i.i.i = call i32 `@bcmp(i8*` nonnull dereferenceable(12) %_11.i.i.i, i8* nonnull dereferenceable(12) %_14.i.i.i, i64 12) #2, !alias.scope !2
  %2 = icmp eq i32 %bcmp.i.i.i, 0
  ret i1 %2
}
```
```x86
playground::demo: # `@playground::demo`
	sub	rsp, 32
	mov	qword ptr [rsp], rdi
	mov	dword ptr [rsp + 8], esi
	mov	qword ptr [rsp + 16], rdx
	mov	dword ptr [rsp + 24], ecx
	xor	rdi, rdx
	xor	esi, ecx
	or	rsi, rdi
	sete	al
	add	rsp, 32
	ret
```

After:
```llvm
define zeroext i1 `@_ZN4mini4demo17h7a8994aaa314c981E(i96` %0, i96 %1) unnamed_addr #0 {
start:
  %2 = icmp eq i96 %0, %1
  ret i1 %2
}
```
```x86
_ZN4mini4demo17h7a8994aaa314c981E:
	xor	rcx, r8
	xor	edx, r9d
	or	rdx, rcx
	sete	al
	ret
```
2021-07-09 09:16:27 +00:00
..
alloc Auto merge of #86982 - GuillaumeGomez:rollup-7sbye3c, r=GuillaumeGomez 2021-07-08 17:51:10 +00:00
backtrace@221483ebaf
core Auto merge of #85828 - scottmcm:raw-eq, r=oli-obk 2021-07-09 09:16:27 +00:00
panic_abort
panic_unwind Remove the deprecated core::raw and std::raw module. 2021-07-03 14:03:27 +08:00
proc_macro Rollup merge of #84029 - drahnr:master, r=petrochenkov 2021-07-03 03:15:07 +09:00
profiler_builtins
rtstartup
rustc-std-workspace-alloc
rustc-std-workspace-core
rustc-std-workspace-std
std Rollup merge of #86726 - sexxi-goose:use-diagnostic-item-for-rfc2229-migration, r=nikomatsakis 2021-07-08 18:30:33 +02:00
stdarch@3001c75a1d
term
test Update to new bootstrap compiler 2021-06-28 11:30:49 -04:00
unwind