800 lines
30 KiB
Rust
800 lines
30 KiB
Rust
//! Codegen of `asm!` invocations.
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use std::fmt::Write;
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use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
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use rustc_span::sym;
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use rustc_target::asm::*;
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use target_lexicon::BinaryFormat;
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use crate::prelude::*;
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pub(crate) enum CInlineAsmOperand<'tcx> {
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In {
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reg: InlineAsmRegOrRegClass,
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value: Value,
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},
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Out {
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reg: InlineAsmRegOrRegClass,
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late: bool,
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place: Option<CPlace<'tcx>>,
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},
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InOut {
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reg: InlineAsmRegOrRegClass,
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_late: bool,
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in_value: Value,
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out_place: Option<CPlace<'tcx>>,
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},
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Const {
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value: String,
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},
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Symbol {
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symbol: String,
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},
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}
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pub(crate) fn codegen_inline_asm_terminator<'tcx>(
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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span: Span,
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template: &[InlineAsmTemplatePiece],
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operands: &[InlineAsmOperand<'tcx>],
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options: InlineAsmOptions,
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destination: Option<mir::BasicBlock>,
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) {
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// Used by panic_abort on Windows, but uses a syntax which only happens to work with
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// asm!() by accident and breaks with the GNU assembler as well as global_asm!() for
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// the LLVM backend.
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if template.len() == 1
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&& template[0] == InlineAsmTemplatePiece::String("int $$0x29".to_string())
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{
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fx.bcx.ins().trap(TrapCode::User(1));
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return;
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}
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let operands = operands
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.iter()
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.map(|operand| match *operand {
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InlineAsmOperand::In { reg, ref value } => CInlineAsmOperand::In {
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reg,
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value: crate::base::codegen_operand(fx, value).load_scalar(fx),
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},
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InlineAsmOperand::Out { reg, late, ref place } => CInlineAsmOperand::Out {
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reg,
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late,
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place: place.map(|place| crate::base::codegen_place(fx, place)),
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},
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InlineAsmOperand::InOut { reg, late, ref in_value, ref out_place } => {
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CInlineAsmOperand::InOut {
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reg,
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_late: late,
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in_value: crate::base::codegen_operand(fx, in_value).load_scalar(fx),
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out_place: out_place.map(|place| crate::base::codegen_place(fx, place)),
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}
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}
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InlineAsmOperand::Const { ref value } => {
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let (const_value, ty) = crate::constant::eval_mir_constant(fx, value);
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let value = rustc_codegen_ssa::common::asm_const_to_str(
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fx.tcx,
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span,
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const_value,
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fx.layout_of(ty),
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);
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CInlineAsmOperand::Const { value }
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}
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InlineAsmOperand::SymFn { ref value } => {
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if cfg!(not(feature = "inline_asm_sym")) {
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fx.tcx
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.dcx()
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.span_err(span, "asm! and global_asm! sym operands are not yet supported");
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}
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let const_ = fx.monomorphize(value.const_);
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if let ty::FnDef(def_id, args) = *const_.ty().kind() {
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let instance = ty::Instance::resolve_for_fn_ptr(
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fx.tcx,
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ty::ParamEnv::reveal_all(),
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def_id,
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args,
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)
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.unwrap();
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let symbol = fx.tcx.symbol_name(instance);
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// Pass a wrapper rather than the function itself as the function itself may not
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// be exported from the main codegen unit and may thus be unreachable from the
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// object file created by an external assembler.
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let inline_asm_index = fx.cx.inline_asm_index.get();
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fx.cx.inline_asm_index.set(inline_asm_index + 1);
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let wrapper_name = format!(
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"__inline_asm_{}_wrapper_n{}",
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fx.cx.cgu_name.as_str().replace('.', "__").replace('-', "_"),
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inline_asm_index
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);
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let sig =
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get_function_sig(fx.tcx, fx.target_config.default_call_conv, instance);
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create_wrapper_function(
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fx.module,
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&mut fx.cx.unwind_context,
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sig,
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&wrapper_name,
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symbol.name,
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);
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CInlineAsmOperand::Symbol { symbol: wrapper_name }
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} else {
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span_bug!(span, "invalid type for asm sym (fn)");
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}
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}
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InlineAsmOperand::SymStatic { def_id } => {
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assert!(fx.tcx.is_static(def_id));
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let instance = Instance::mono(fx.tcx, def_id).polymorphize(fx.tcx);
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CInlineAsmOperand::Symbol { symbol: fx.tcx.symbol_name(instance).name.to_owned() }
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}
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InlineAsmOperand::Label { .. } => {
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span_bug!(span, "asm! label operands are not yet supported");
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}
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})
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.collect::<Vec<_>>();
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codegen_inline_asm_inner(fx, template, &operands, options);
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match destination {
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Some(destination) => {
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let destination_block = fx.get_block(destination);
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fx.bcx.ins().jump(destination_block, &[]);
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}
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None => {
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fx.bcx.ins().trap(TrapCode::UnreachableCodeReached);
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}
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}
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}
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pub(crate) fn codegen_inline_asm_inner<'tcx>(
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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template: &[InlineAsmTemplatePiece],
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operands: &[CInlineAsmOperand<'tcx>],
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options: InlineAsmOptions,
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) {
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// FIXME add .eh_frame unwind info directives
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let mut asm_gen = InlineAssemblyGenerator {
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tcx: fx.tcx,
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arch: fx.tcx.sess.asm_arch.unwrap(),
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enclosing_def_id: fx.instance.def_id(),
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template,
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operands,
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options,
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registers: Vec::new(),
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stack_slots_clobber: Vec::new(),
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stack_slots_input: Vec::new(),
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stack_slots_output: Vec::new(),
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stack_slot_size: Size::from_bytes(0),
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};
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asm_gen.allocate_registers();
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asm_gen.allocate_stack_slots();
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let inline_asm_index = fx.cx.inline_asm_index.get();
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fx.cx.inline_asm_index.set(inline_asm_index + 1);
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let asm_name = format!(
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"__inline_asm_{}_n{}",
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fx.cx.cgu_name.as_str().replace('.', "__").replace('-', "_"),
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inline_asm_index
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);
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let generated_asm = asm_gen.generate_asm_wrapper(&asm_name);
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fx.cx.global_asm.push_str(&generated_asm);
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let mut inputs = Vec::new();
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let mut outputs = Vec::new();
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for (i, operand) in operands.iter().enumerate() {
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match operand {
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CInlineAsmOperand::In { reg: _, value } => {
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inputs.push((asm_gen.stack_slots_input[i].unwrap(), *value));
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}
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CInlineAsmOperand::Out { reg: _, late: _, place } => {
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if let Some(place) = place {
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outputs.push((asm_gen.stack_slots_output[i].unwrap(), *place));
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}
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}
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CInlineAsmOperand::InOut { reg: _, _late: _, in_value, out_place } => {
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inputs.push((asm_gen.stack_slots_input[i].unwrap(), *in_value));
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if let Some(out_place) = out_place {
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outputs.push((asm_gen.stack_slots_output[i].unwrap(), *out_place));
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}
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}
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CInlineAsmOperand::Const { value: _ } | CInlineAsmOperand::Symbol { symbol: _ } => {}
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}
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}
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call_inline_asm(fx, &asm_name, asm_gen.stack_slot_size, inputs, outputs);
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}
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struct InlineAssemblyGenerator<'a, 'tcx> {
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tcx: TyCtxt<'tcx>,
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arch: InlineAsmArch,
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enclosing_def_id: DefId,
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template: &'a [InlineAsmTemplatePiece],
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operands: &'a [CInlineAsmOperand<'tcx>],
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options: InlineAsmOptions,
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registers: Vec<Option<InlineAsmReg>>,
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stack_slots_clobber: Vec<Option<Size>>,
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stack_slots_input: Vec<Option<Size>>,
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stack_slots_output: Vec<Option<Size>>,
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stack_slot_size: Size,
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}
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impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
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fn allocate_registers(&mut self) {
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let sess = self.tcx.sess;
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let map = allocatable_registers(
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self.arch,
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sess.relocation_model(),
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self.tcx.asm_target_features(self.enclosing_def_id),
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&sess.target,
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);
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let mut allocated = FxHashMap::<_, (bool, bool)>::default();
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let mut regs = vec![None; self.operands.len()];
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// Add explicit registers to the allocated set.
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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CInlineAsmOperand::In { reg: InlineAsmRegOrRegClass::Reg(reg), .. } => {
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regs[i] = Some(reg);
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allocated.entry(reg).or_default().0 = true;
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}
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CInlineAsmOperand::Out {
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reg: InlineAsmRegOrRegClass::Reg(reg),
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late: true,
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..
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} => {
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regs[i] = Some(reg);
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allocated.entry(reg).or_default().1 = true;
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}
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CInlineAsmOperand::Out { reg: InlineAsmRegOrRegClass::Reg(reg), .. }
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| CInlineAsmOperand::InOut { reg: InlineAsmRegOrRegClass::Reg(reg), .. } => {
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regs[i] = Some(reg);
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allocated.insert(reg, (true, true));
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}
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_ => (),
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}
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}
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// Allocate out/inout/inlateout registers first because they are more constrained.
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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CInlineAsmOperand::Out {
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reg: InlineAsmRegOrRegClass::RegClass(class),
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late: false,
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..
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}
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| CInlineAsmOperand::InOut {
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reg: InlineAsmRegOrRegClass::RegClass(class), ..
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} => {
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let mut alloc_reg = None;
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for ® in &map[&class] {
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let mut used = false;
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reg.overlapping_regs(|r| {
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if allocated.contains_key(&r) {
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used = true;
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}
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});
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if !used {
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alloc_reg = Some(reg);
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break;
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}
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}
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let reg = alloc_reg.expect("cannot allocate registers");
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regs[i] = Some(reg);
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allocated.insert(reg, (true, true));
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}
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_ => (),
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}
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}
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// Allocate in/lateout.
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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CInlineAsmOperand::In { reg: InlineAsmRegOrRegClass::RegClass(class), .. } => {
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let mut alloc_reg = None;
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for ® in &map[&class] {
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let mut used = false;
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reg.overlapping_regs(|r| {
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if allocated.get(&r).copied().unwrap_or_default().0 {
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used = true;
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}
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});
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if !used {
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alloc_reg = Some(reg);
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break;
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}
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}
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let reg = alloc_reg.expect("cannot allocate registers");
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regs[i] = Some(reg);
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allocated.entry(reg).or_default().0 = true;
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}
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CInlineAsmOperand::Out {
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reg: InlineAsmRegOrRegClass::RegClass(class),
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late: true,
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..
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} => {
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let mut alloc_reg = None;
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for ® in &map[&class] {
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let mut used = false;
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reg.overlapping_regs(|r| {
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if allocated.get(&r).copied().unwrap_or_default().1 {
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used = true;
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}
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});
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if !used {
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alloc_reg = Some(reg);
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break;
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}
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}
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let reg = alloc_reg.expect("cannot allocate registers");
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regs[i] = Some(reg);
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allocated.entry(reg).or_default().1 = true;
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}
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_ => (),
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}
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}
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self.registers = regs;
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}
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fn allocate_stack_slots(&mut self) {
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let mut slot_size = Size::from_bytes(0);
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let mut slots_clobber = vec![None; self.operands.len()];
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let mut slots_input = vec![None; self.operands.len()];
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let mut slots_output = vec![None; self.operands.len()];
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let new_slot_fn = |slot_size: &mut Size, reg_class: InlineAsmRegClass| {
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let reg_size =
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reg_class.supported_types(self.arch).iter().map(|(ty, _)| ty.size()).max().unwrap();
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let align = rustc_target::abi::Align::from_bytes(reg_size.bytes()).unwrap();
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let offset = slot_size.align_to(align);
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*slot_size = offset + reg_size;
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offset
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};
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let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
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// Allocate stack slots for saving clobbered registers
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let abi_clobber = InlineAsmClobberAbi::parse(self.arch, &self.tcx.sess.target, sym::C)
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.unwrap()
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.clobbered_regs();
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for (i, reg) in self.registers.iter().enumerate().filter_map(|(i, r)| r.map(|r| (i, r))) {
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let mut need_save = true;
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// If the register overlaps with a register clobbered by function call, then
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// we don't need to save it.
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for r in abi_clobber {
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r.overlapping_regs(|r| {
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if r == reg {
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need_save = false;
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}
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});
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if !need_save {
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break;
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}
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}
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if need_save {
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slots_clobber[i] = Some(new_slot(reg.reg_class()));
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}
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}
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// Allocate stack slots for inout
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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CInlineAsmOperand::InOut { reg, out_place: Some(_), .. } => {
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let slot = new_slot(reg.reg_class());
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slots_input[i] = Some(slot);
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slots_output[i] = Some(slot);
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}
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_ => (),
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}
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}
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let slot_size_before_input = slot_size;
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let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
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// Allocate stack slots for input
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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CInlineAsmOperand::In { reg, .. }
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| CInlineAsmOperand::InOut { reg, out_place: None, .. } => {
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slots_input[i] = Some(new_slot(reg.reg_class()));
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}
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_ => (),
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}
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}
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// Reset slot size to before input so that input and output operands can overlap
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// and save some memory.
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let slot_size_after_input = slot_size;
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slot_size = slot_size_before_input;
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let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
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// Allocate stack slots for output
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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CInlineAsmOperand::Out { reg, place: Some(_), .. } => {
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slots_output[i] = Some(new_slot(reg.reg_class()));
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}
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_ => (),
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}
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}
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slot_size = slot_size.max(slot_size_after_input);
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self.stack_slots_clobber = slots_clobber;
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self.stack_slots_input = slots_input;
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self.stack_slots_output = slots_output;
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self.stack_slot_size = slot_size;
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}
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fn generate_asm_wrapper(&self, asm_name: &str) -> String {
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let binary_format = crate::target_triple(self.tcx.sess).binary_format;
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let mut generated_asm = String::new();
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match binary_format {
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BinaryFormat::Elf => {
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writeln!(generated_asm, ".globl {}", asm_name).unwrap();
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writeln!(generated_asm, ".type {},@function", asm_name).unwrap();
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writeln!(generated_asm, ".section .text.{},\"ax\",@progbits", asm_name).unwrap();
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writeln!(generated_asm, "{}:", asm_name).unwrap();
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}
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BinaryFormat::Macho => {
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writeln!(generated_asm, ".globl _{}", asm_name).unwrap();
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writeln!(generated_asm, "_{}:", asm_name).unwrap();
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}
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BinaryFormat::Coff => {
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writeln!(generated_asm, ".globl {}", asm_name).unwrap();
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writeln!(generated_asm, "{}:", asm_name).unwrap();
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}
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_ => self
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.tcx
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.dcx()
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.fatal(format!("Unsupported binary format for inline asm: {binary_format:?}")),
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}
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let is_x86 = matches!(self.arch, InlineAsmArch::X86 | InlineAsmArch::X86_64);
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if is_x86 {
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generated_asm.push_str(".intel_syntax noprefix\n");
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}
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Self::prologue(&mut generated_asm, self.arch);
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// Save clobbered registers
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if !self.options.contains(InlineAsmOptions::NORETURN) {
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for (reg, slot) in self
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.registers
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.iter()
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.zip(self.stack_slots_clobber.iter().copied())
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.filter_map(|(r, s)| r.zip(s))
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{
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Self::save_register(&mut generated_asm, self.arch, reg, slot);
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}
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}
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// Write input registers
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for (reg, slot) in self
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.registers
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.iter()
|
|
.zip(self.stack_slots_input.iter().copied())
|
|
.filter_map(|(r, s)| r.zip(s))
|
|
{
|
|
Self::restore_register(&mut generated_asm, self.arch, reg, slot);
|
|
}
|
|
|
|
if is_x86 && self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
|
|
generated_asm.push_str(".att_syntax\n");
|
|
}
|
|
|
|
// The actual inline asm
|
|
for piece in self.template {
|
|
match piece {
|
|
InlineAsmTemplatePiece::String(s) => {
|
|
generated_asm.push_str(s);
|
|
}
|
|
InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
|
|
match self.operands[*operand_idx] {
|
|
CInlineAsmOperand::In { .. }
|
|
| CInlineAsmOperand::Out { .. }
|
|
| CInlineAsmOperand::InOut { .. } => {
|
|
if self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
|
|
generated_asm.push('%');
|
|
}
|
|
|
|
let reg = self.registers[*operand_idx].unwrap();
|
|
match self.arch {
|
|
InlineAsmArch::X86_64 => match reg {
|
|
InlineAsmReg::X86(reg)
|
|
if reg as u32 >= X86InlineAsmReg::xmm0 as u32
|
|
&& reg as u32 <= X86InlineAsmReg::xmm15 as u32 =>
|
|
{
|
|
// rustc emits x0 rather than xmm0
|
|
let class = match *modifier {
|
|
None | Some('x') => "xmm",
|
|
Some('y') => "ymm",
|
|
Some('z') => "zmm",
|
|
_ => unreachable!(),
|
|
};
|
|
write!(
|
|
generated_asm,
|
|
"{class}{}",
|
|
reg as u32 - X86InlineAsmReg::xmm0 as u32
|
|
)
|
|
.unwrap();
|
|
}
|
|
_ => reg
|
|
.emit(&mut generated_asm, InlineAsmArch::X86_64, *modifier)
|
|
.unwrap(),
|
|
},
|
|
_ => reg.emit(&mut generated_asm, self.arch, *modifier).unwrap(),
|
|
}
|
|
}
|
|
CInlineAsmOperand::Const { ref value } => {
|
|
generated_asm.push_str(value);
|
|
}
|
|
CInlineAsmOperand::Symbol { ref symbol } => generated_asm.push_str(symbol),
|
|
}
|
|
}
|
|
}
|
|
}
|
|
generated_asm.push('\n');
|
|
|
|
if is_x86 && self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
|
|
generated_asm.push_str(".intel_syntax noprefix\n");
|
|
}
|
|
|
|
if !self.options.contains(InlineAsmOptions::NORETURN) {
|
|
// Read output registers
|
|
for (reg, slot) in self
|
|
.registers
|
|
.iter()
|
|
.zip(self.stack_slots_output.iter().copied())
|
|
.filter_map(|(r, s)| r.zip(s))
|
|
{
|
|
Self::save_register(&mut generated_asm, self.arch, reg, slot);
|
|
}
|
|
|
|
// Restore clobbered registers
|
|
for (reg, slot) in self
|
|
.registers
|
|
.iter()
|
|
.zip(self.stack_slots_clobber.iter().copied())
|
|
.filter_map(|(r, s)| r.zip(s))
|
|
{
|
|
Self::restore_register(&mut generated_asm, self.arch, reg, slot);
|
|
}
|
|
|
|
Self::epilogue(&mut generated_asm, self.arch);
|
|
} else {
|
|
Self::epilogue_noreturn(&mut generated_asm, self.arch);
|
|
}
|
|
|
|
if is_x86 {
|
|
generated_asm.push_str(".att_syntax\n");
|
|
}
|
|
|
|
match binary_format {
|
|
BinaryFormat::Elf => {
|
|
writeln!(generated_asm, ".size {name}, .-{name}", name = asm_name).unwrap();
|
|
generated_asm.push_str(".text\n");
|
|
}
|
|
BinaryFormat::Macho | BinaryFormat::Coff => {}
|
|
_ => self
|
|
.tcx
|
|
.dcx()
|
|
.fatal(format!("Unsupported binary format for inline asm: {binary_format:?}")),
|
|
}
|
|
|
|
generated_asm.push_str("\n\n");
|
|
|
|
generated_asm
|
|
}
|
|
|
|
fn prologue(generated_asm: &mut String, arch: InlineAsmArch) {
|
|
match arch {
|
|
InlineAsmArch::X86_64 => {
|
|
generated_asm.push_str(" push rbp\n");
|
|
generated_asm.push_str(" mov rbp,rsp\n");
|
|
generated_asm.push_str(" push rbx\n"); // rbx is callee saved
|
|
// rbx is reserved by LLVM for the "base pointer", so rustc doesn't allow using it
|
|
generated_asm.push_str(" mov rbx,rdi\n");
|
|
}
|
|
InlineAsmArch::AArch64 => {
|
|
generated_asm.push_str(" stp fp, lr, [sp, #-32]!\n");
|
|
generated_asm.push_str(" mov fp, sp\n");
|
|
generated_asm.push_str(" str x19, [sp, #24]\n"); // x19 is callee saved
|
|
// x19 is reserved by LLVM for the "base pointer", so rustc doesn't allow using it
|
|
generated_asm.push_str(" mov x19, x0\n");
|
|
}
|
|
InlineAsmArch::RiscV64 => {
|
|
generated_asm.push_str(" addi sp, sp, -16\n");
|
|
generated_asm.push_str(" sd ra, 8(sp)\n");
|
|
generated_asm.push_str(" sd s1, 0(sp)\n"); // s1 is callee saved
|
|
// s1/x9 is reserved by LLVM for the "base pointer", so rustc doesn't allow using it
|
|
generated_asm.push_str(" mv s1, a0\n");
|
|
}
|
|
_ => unimplemented!("prologue for {:?}", arch),
|
|
}
|
|
}
|
|
|
|
fn epilogue(generated_asm: &mut String, arch: InlineAsmArch) {
|
|
match arch {
|
|
InlineAsmArch::X86_64 => {
|
|
generated_asm.push_str(" pop rbx\n");
|
|
generated_asm.push_str(" pop rbp\n");
|
|
generated_asm.push_str(" ret\n");
|
|
}
|
|
InlineAsmArch::AArch64 => {
|
|
generated_asm.push_str(" ldr x19, [sp, #24]\n");
|
|
generated_asm.push_str(" ldp fp, lr, [sp], #32\n");
|
|
generated_asm.push_str(" ret\n");
|
|
}
|
|
InlineAsmArch::RiscV64 => {
|
|
generated_asm.push_str(" ld s1, 0(sp)\n");
|
|
generated_asm.push_str(" ld ra, 8(sp)\n");
|
|
generated_asm.push_str(" addi sp, sp, 16\n");
|
|
generated_asm.push_str(" ret\n");
|
|
}
|
|
_ => unimplemented!("epilogue for {:?}", arch),
|
|
}
|
|
}
|
|
|
|
fn epilogue_noreturn(generated_asm: &mut String, arch: InlineAsmArch) {
|
|
match arch {
|
|
InlineAsmArch::X86_64 => {
|
|
generated_asm.push_str(" ud2\n");
|
|
}
|
|
InlineAsmArch::AArch64 => {
|
|
generated_asm.push_str(" brk #0x1\n");
|
|
}
|
|
InlineAsmArch::RiscV64 => {
|
|
generated_asm.push_str(" ebreak\n");
|
|
}
|
|
_ => unimplemented!("epilogue_noreturn for {:?}", arch),
|
|
}
|
|
}
|
|
|
|
fn save_register(
|
|
generated_asm: &mut String,
|
|
arch: InlineAsmArch,
|
|
reg: InlineAsmReg,
|
|
offset: Size,
|
|
) {
|
|
match arch {
|
|
InlineAsmArch::X86_64 => {
|
|
match reg {
|
|
InlineAsmReg::X86(reg)
|
|
if reg as u32 >= X86InlineAsmReg::xmm0 as u32
|
|
&& reg as u32 <= X86InlineAsmReg::xmm15 as u32 =>
|
|
{
|
|
// rustc emits x0 rather than xmm0
|
|
write!(generated_asm, " movups [rbx+0x{:x}], ", offset.bytes()).unwrap();
|
|
write!(generated_asm, "xmm{}", reg as u32 - X86InlineAsmReg::xmm0 as u32)
|
|
.unwrap();
|
|
}
|
|
_ => {
|
|
write!(generated_asm, " mov [rbx+0x{:x}], ", offset.bytes()).unwrap();
|
|
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
|
|
}
|
|
}
|
|
generated_asm.push('\n');
|
|
}
|
|
InlineAsmArch::AArch64 => {
|
|
generated_asm.push_str(" str ");
|
|
reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap();
|
|
writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap();
|
|
}
|
|
InlineAsmArch::RiscV64 => {
|
|
generated_asm.push_str(" sd ");
|
|
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
|
|
writeln!(generated_asm, ", 0x{:x}(s1)", offset.bytes()).unwrap();
|
|
}
|
|
_ => unimplemented!("save_register for {:?}", arch),
|
|
}
|
|
}
|
|
|
|
fn restore_register(
|
|
generated_asm: &mut String,
|
|
arch: InlineAsmArch,
|
|
reg: InlineAsmReg,
|
|
offset: Size,
|
|
) {
|
|
match arch {
|
|
InlineAsmArch::X86_64 => {
|
|
match reg {
|
|
InlineAsmReg::X86(reg)
|
|
if reg as u32 >= X86InlineAsmReg::xmm0 as u32
|
|
&& reg as u32 <= X86InlineAsmReg::xmm15 as u32 =>
|
|
{
|
|
// rustc emits x0 rather than xmm0
|
|
write!(
|
|
generated_asm,
|
|
" movups xmm{}",
|
|
reg as u32 - X86InlineAsmReg::xmm0 as u32
|
|
)
|
|
.unwrap();
|
|
}
|
|
_ => {
|
|
generated_asm.push_str(" mov ");
|
|
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap()
|
|
}
|
|
}
|
|
writeln!(generated_asm, ", [rbx+0x{:x}]", offset.bytes()).unwrap();
|
|
}
|
|
InlineAsmArch::AArch64 => {
|
|
generated_asm.push_str(" ldr ");
|
|
reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap();
|
|
writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap();
|
|
}
|
|
InlineAsmArch::RiscV64 => {
|
|
generated_asm.push_str(" ld ");
|
|
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
|
|
writeln!(generated_asm, ", 0x{:x}(s1)", offset.bytes()).unwrap();
|
|
}
|
|
_ => unimplemented!("restore_register for {:?}", arch),
|
|
}
|
|
}
|
|
}
|
|
|
|
fn call_inline_asm<'tcx>(
|
|
fx: &mut FunctionCx<'_, '_, 'tcx>,
|
|
asm_name: &str,
|
|
slot_size: Size,
|
|
inputs: Vec<(Size, Value)>,
|
|
outputs: Vec<(Size, CPlace<'tcx>)>,
|
|
) {
|
|
let stack_slot = fx.create_stack_slot(u32::try_from(slot_size.bytes()).unwrap(), 16);
|
|
|
|
let inline_asm_func = fx
|
|
.module
|
|
.declare_function(
|
|
asm_name,
|
|
Linkage::Import,
|
|
&Signature {
|
|
call_conv: CallConv::SystemV,
|
|
params: vec![AbiParam::new(fx.pointer_type)],
|
|
returns: vec![],
|
|
},
|
|
)
|
|
.unwrap();
|
|
let inline_asm_func = fx.module.declare_func_in_func(inline_asm_func, fx.bcx.func);
|
|
if fx.clif_comments.enabled() {
|
|
fx.add_comment(inline_asm_func, asm_name);
|
|
}
|
|
|
|
for (offset, value) in inputs {
|
|
stack_slot.offset(fx, i32::try_from(offset.bytes()).unwrap().into()).store(
|
|
fx,
|
|
value,
|
|
MemFlags::trusted(),
|
|
);
|
|
}
|
|
|
|
let stack_slot_addr = stack_slot.get_addr(fx);
|
|
fx.bcx.ins().call(inline_asm_func, &[stack_slot_addr]);
|
|
|
|
for (offset, place) in outputs {
|
|
let ty = if place.layout().ty.is_simd() {
|
|
let (lane_count, lane_type) = place.layout().ty.simd_size_and_type(fx.tcx);
|
|
fx.clif_type(lane_type).unwrap().by(lane_count.try_into().unwrap()).unwrap()
|
|
} else {
|
|
fx.clif_type(place.layout().ty).unwrap()
|
|
};
|
|
let value = stack_slot.offset(fx, i32::try_from(offset.bytes()).unwrap().into()).load(
|
|
fx,
|
|
ty,
|
|
MemFlags::trusted(),
|
|
);
|
|
place.write_cvalue(fx, CValue::by_val(value, place.layout()));
|
|
}
|
|
}
|