a2a1206811
Return values larger than 2 registers using a return area pointer
LLVM and Cranelift disagree about how to return values that don't fit in the registers designated for return values. LLVM will force the entire return value to be passed by return area pointer, while Cranelift will look at each IR level return value independently and decide to pass it in a register or not, which would result in the return value being passed partially in registers and partially through a return area pointer.
While Cranelift may need to be fixed as the LLVM behavior is generally more correct with respect to the surface language, forcing this behavior in rustc itself makes it easier for other backends to conform to the Rust ABI and for the C ABI rustc already handles this behavior anyway.
In addition LLVM's decision to pass the return value in registers or using a return area pointer depends on how exactly the return type is lowered to an LLVM IR type. For example `Option<u128>` can be lowered as `{ i128, i128 }` in which case the x86_64 backend would use a return area pointer, or it could be passed as `{ i32, i128 }` in which case the x86_64 backend would pass it in registers by taking advantage of an LLVM ABI extension that allows using 3 registers for the x86_64 sysv call conv rather than the officially specified 2 registers.
This adjustment is only necessary for the Rust ABI as for other ABI's the calling convention implementations in rustc_target already ensure any return value which doesn't fit in the available amount of return registers is passed in the right way for the current target.
Helps with https://github.com/rust-lang/rustc_codegen_cranelift/issues/1525
cc https://github.com/bytecodealliance/wasmtime/issues/9250
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| .. | ||
| asm | ||
| auxiliary | ||
| libs | ||
| nvptx-kernel-abi | ||
| simd | ||
| stack-protector | ||
| targets | ||
| aarch64-naked-fn-no-bti-prolog.rs | ||
| aarch64-pointer-auth.rs | ||
| align_offset.rs | ||
| asm-comments.rs | ||
| closure-inherit-target-feature.rs | ||
| cmse.rs | ||
| dwarf4.rs | ||
| dwarf5.rs | ||
| is_aligned.rs | ||
| issue-83585-small-pod-struct-equality.rs | ||
| manual-eq-efficient.rs | ||
| niche-prefer-zero.rs | ||
| nvptx-arch-default.rs | ||
| nvptx-arch-emit-asm.rs | ||
| nvptx-arch-link-arg.rs | ||
| nvptx-arch-target-cpu.rs | ||
| nvptx-atomics.rs | ||
| nvptx-c-abi-arg-v7.rs | ||
| nvptx-c-abi-ret-v7.rs | ||
| nvptx-internalizing.rs | ||
| nvptx-linking-binary.rs | ||
| nvptx-linking-cdylib.rs | ||
| nvptx-safe-naming.rs | ||
| panic-no-unwind-no-uwtable.rs | ||
| panic-unwind-no-uwtable.rs | ||
| pic-relocation-model.rs | ||
| pie-relocation-model.rs | ||
| powerpc64-struct-abi.rs | ||
| s390x-backchain-toggle.rs | ||
| simd-bitmask.rs | ||
| simd-intrinsic-gather.rs | ||
| simd-intrinsic-mask-load.rs | ||
| simd-intrinsic-mask-reduce.rs | ||
| simd-intrinsic-mask-store.rs | ||
| simd-intrinsic-scatter.rs | ||
| simd-intrinsic-select.rs | ||
| slice-is_ascii.rs | ||
| small_data_threshold.rs | ||
| sparc-struct-abi.rs | ||
| stack-probes.rs | ||
| static-relocation-model.rs | ||
| strict_provenance.rs | ||
| target-feature-multiple.rs | ||
| wasm_exceptions.rs | ||
| x86_64-array-pair-load-store-merge.rs | ||
| x86_64-cmp.rs | ||
| x86_64-floating-point-clamp.rs | ||
| x86_64-fortanix-unknown-sgx-lvi-generic-load.rs | ||
| x86_64-fortanix-unknown-sgx-lvi-generic-ret.rs | ||
| x86_64-fortanix-unknown-sgx-lvi-inline-assembly.rs | ||
| x86_64-function-return.rs | ||
| x86_64-naked-fn-no-cet-prolog.rs | ||
| x86_64-no-jump-tables.rs | ||
| x86_64-sse_crc.rs | ||
| x86_64-typed-swap.rs | ||
| x86_64-windows-float-abi.rs | ||
| x86-return-float.rs | ||