rust/src/librustc_data_structures
bors 05a7f25cc4 Auto merge of #39456 - nagisa:mir-switchint-everywhere, r=nikomatsakis
[MIR] SwitchInt Everywhere

Something I've been meaning to do for a very long while. This PR essentially gets rid of 3 kinds of conditional branching and only keeps the most general one - `SwitchInt`. Primary benefits are such that dealing with MIR now does not involve dealing with 3 different ways to do conditional control flow. On the other hand, constructing a `SwitchInt` currently requires more code than what previously was necessary to build an equivalent `If` terminator. Something trivially "fixable" with some constructor methods somewhere (MIR needs stuff like that badly in general).

Some timings (tl;dr: slightly faster^1 (unexpected), but also uses slightly more memory at peak (expected)):

^1: Not sure if the speed benefits are because of LLVM liking the generated code better or the compiler itself getting compiled better. Either way, its a net benefit. The CORE and SYNTAX timings done for compilation without optimisation.

```
AFTER:
Building stage1 std artifacts (x86_64-unknown-linux-gnu -> x86_64-unknown-linux-gnu)
    Finished release [optimized] target(s) in 31.50 secs
    Finished release [optimized] target(s) in 31.42 secs
Building stage1 compiler artifacts (x86_64-unknown-linux-gnu -> x86_64-unknown-linux-gnu)
    Finished release [optimized] target(s) in 439.56 secs
    Finished release [optimized] target(s) in 435.15 secs

CORE: 99% (24.81 real, 0.13 kernel, 24.57 user); 358536k resident
CORE: 99% (24.56 real, 0.15 kernel, 24.36 user); 359168k resident
SYNTAX: 99% (49.98 real, 0.48 kernel, 49.42 user); 653416k resident
SYNTAX: 99% (50.07 real, 0.58 kernel, 49.43 user); 653604k resident

BEFORE:
Building stage1 std artifacts (x86_64-unknown-linux-gnu -> x86_64-unknown-linux-gnu)
    Finished release [optimized] target(s) in 31.84 secs
Building stage1 compiler artifacts (x86_64-unknown-linux-gnu -> x86_64-unknown-linux-gnu)
    Finished release [optimized] target(s) in 451.17 secs

CORE: 99% (24.66 real, 0.20 kernel, 24.38 user); 351096k resident
CORE: 99% (24.36 real, 0.17 kernel, 24.18 user); 352284k resident
SYNTAX: 99% (52.24 real, 0.56 kernel, 51.66 user); 645544k resident
SYNTAX: 99% (51.55 real, 0.48 kernel, 50.99 user); 646428k resident
```

cc @nikomatsakis @eddyb
2017-02-13 02:32:09 +00:00
..
control_flow_graph
graph
obligation_forest
snapshot_map
unify
veccell
accumulate_vec.rs Remove dead recursive partial eq impl 2017-01-29 06:07:45 +01:00
array_vec.rs Remove dead recursive partial eq impl 2017-01-29 06:07:45 +01:00
base_n.rs
bitslice.rs
bitvec.rs SwitchInt over Switch 2017-02-10 19:42:41 +02:00
blake2b.rs Use little-endian encoding for Blake2 hashing on all architectures 2017-01-10 20:43:32 +02:00
Cargo.toml Bump version, upgrade bootstrap 2017-02-03 13:25:46 -08:00
flock.rs Allow rustc data structures compile to android 2017-02-10 16:34:10 -02:00
fmt_wrap.rs
fnv.rs
fx.rs
indexed_set.rs
indexed_vec.rs
ivar.rs
lib.rs Bump version, upgrade bootstrap 2017-02-03 13:25:46 -08:00
small_vec.rs
snapshot_vec.rs
stable_hasher.rs Bump version, upgrade bootstrap 2017-02-03 13:25:46 -08:00
transitive_relation.rs
tuple_slice.rs