42 lines
2.4 KiB
Rust
42 lines
2.4 KiB
Rust
// MIR for `ilog2` after PreCodegen
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fn ilog2(_1: u32) -> u32 {
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debug x => _1; // in scope 0 at $DIR/checked_ops.rs:+0:14: +0:15
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let mut _0: u32; // return place in scope 0 at $DIR/checked_ops.rs:+0:25: +0:28
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scope 1 (inlined #[track_caller] core::num::<impl u32>::ilog2) { // at $DIR/checked_ops.rs:19:7: 19:14
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debug self => _1; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _2: std::option::Option<u32>; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _3: isize; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _4: !; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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scope 2 {
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debug log => _0; // in scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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}
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}
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bb0: {
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StorageLive(_2); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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_2 = core::num::<impl u32>::checked_ilog2(_1) -> bb1; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// mir::Constant
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// + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// + literal: Const { ty: fn(u32) -> Option<u32> {core::num::<impl u32>::checked_ilog2}, val: Value(<ZST>) }
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}
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bb1: {
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_3 = discriminant(_2); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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switchInt(move _3) -> [1: bb2, otherwise: bb3]; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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}
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bb2: {
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_0 = ((_2 as Some).0: u32); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_2); // scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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return; // scope 0 at $DIR/checked_ops.rs:+2:2: +2:2
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}
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bb3: {
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_4 = core::num::int_log10::panic_for_nonpositive_argument(); // scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// mir::Constant
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// + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// + literal: Const { ty: fn() -> ! {core::num::int_log10::panic_for_nonpositive_argument}, val: Value(<ZST>) }
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}
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}
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