8 Commits

Author	SHA1	Message	Date
Guillaume Gomez	cede91971a	Add tools/llvmint-2 to ignored entries	2022-05-15 15:31:25 +02:00
Guillaume Gomez	19d8617330	Generate intrinsics translations from llvmint as well	2022-05-03 21:24:14 +02:00
Guillaume Gomez	af9149a1c6	Add tool to generate intrinsics conversion automatically	2022-05-03 18:59:04 +02:00
Antoni Boucher	02970a6ca8	Add support for target builtins	2022-03-29 21:41:17 -04:00
antoyo	41f20fa3a5	Support 128-bit integers on platforms without native support (#103) ... * Use sized integer types * Add support for integer types not supported on some platforms * Add feature to test non-native integers in CI	2022-01-30 21:45:14 -05:00
Commeownist	7c707e4b95	Implement basic inline asm support (#72) ... * Implement basic support for inline assembly * Disable LTO We don't support it yet at all * Handle `inout(reg) var` correctly Turns out that `+` readwrite output registers cannot be tied with input variables. * Add limited support for llvm_asm! * Handle CHANNEL correctly * Add support for arbitrary explicit registers * Handle symbols properly * Add rudimentary asm tests * Exclude llvm_asm! tests from tests runs * Insert `__builtin_unreachable()` after diverging asm blocks	2021-09-05 11:26:01 -04:00
antoyo	5dad13cc3b	Update custom rustc instructions (#73)	2021-08-28 11:34:47 -04:00
Antoni Boucher	afae271d5d	Initial commit	2021-08-12 21:46:50 -04:00