23 Commits

Author SHA1 Message Date
Alessandro Decina
b2a6967114 Add support for BPF inline assembly 2021-05-23 18:03:27 +10:00
bors
fe72845f7b Auto merge of #85312 - ehuss:macro_use-unused-attr, r=petrochenkov
Fix unused attributes on macro_rules.

The `unused_attributes` lint wasn't firing on attributes of `macro_rules` definitions. The consequence is that many attributes are silently ignored on `macro_rules`. The reason is that `unused_attributes` is a late-lint pass, and only has access to the HIR, which does not have macro_rules definitions.

My solution here is to change `non_exported_macro_attrs` to be `macro_attrs` (a list of all attributes used for `macro_rules`, instead of just those for `macro_export`), and then to check this list in the `unused_attributes` lint. There are a number of alternate approaches, but this seemed the most reliable and least invasive. I am open to completely different approaches, though.

One concern is that I don't fully understand the implications of extending `non_exported_macro_attrs` to include non-exported macros. That list was originally added in #62042 to handle stability attributes, so I suspect it was just an optimization since that was all that was needed. It was later extended to be included in SVH in #83901. #80641 also added a use to check for `invalid` attributes, which seems a little odd to me (it didn't validate non-exported macros, and seems highly specific).

Overall, there doesn't seem to be a clear story of when `unused_attributes` should be used versus an error like E0518. I considered alternatively using an "allow list" of built-in attributes that can be used on macro_rules (allow, warn, deny, forbid, cfg, cfg_attr, macro_export, deprecated, doc), but I feel like that could be a pain to maintain.

Some built-in attributes already present hard-errors when used with macro_rules. These are each hard-coded in various places:
- `derive`
- `test` and `bench`
- `proc_macro` and `proc_macro_derive`
- `inline`
- `global_allocator`

The primary motivation is that I sometimes see people use `#[macro_use]` in front of `macro_rules`, which indicates there is some confusion out there (evident that there was even a case of it in rustc).
2021-05-16 20:19:45 +00:00
Eric Huss
5bbc240ffb Fix unused attributes on macro_rules. 2021-05-15 16:13:46 -07:00
Dr. Chat
69acee3ffe Add asm!() support for PowerPC64 2021-05-13 22:31:47 -05:00
Dr. Chat
b1bb5d662c Add initial asm!() support for PowerPC
This includes GPRs and FPRs only
2021-05-11 19:04:16 -05:00
Amanieu d'Antras
ea310d9253 Reserve x18 on AArch64 and un-reserve x16 2021-05-01 13:25:56 +01:00
Amanieu d'Antras
e6a731eb90 Be stricter about rejecting LLVM reserved registers in asm! 2021-04-28 18:30:36 +01:00
Amanieu d'Antras
b1bcff0731 Disallow the use of high byte registes as operands on x86_64
They are still allowed on x86 though.

Fixes #83495
2021-04-05 13:38:24 +01:00
Amanieu d'Antras
ba00ddc39a Address review comments 2021-03-14 23:21:03 +00:00
Amanieu d'Antras
fa3694fada Always lower asm! to valid HIR 2021-03-13 20:49:32 +00:00
Simon Vandel Sillesen
2d1e0adfe9 New pass to deduplicate blocks 2021-02-21 21:51:54 +01:00
Arlie Davis
40ed0f6857 Use Symbol for inline asm register class names
This takes care of one "FIXME":
// FIXME: use direct symbol comparison for register class names

Instead of using string literals, this uses Symbol for register
class names.
2020-12-10 13:51:56 -08:00
Gus Caplan
d9f237caa6
Add wasm32 support to inline asm 2020-12-01 12:18:21 -06:00
Mara Bos
76fa5f25ab
Rollup merge of #78950 - khyperia:spirv-asm, r=Amanieu
Add asm register information for SPIR-V

As discussed in [zulip](https://rust-lang.zulipchat.com/#narrow/stream/182449-t-compiler.2Fhelp/topic/Defining.20asm!.20for.20new.20architecture), we at [rust-gpu](https://github.com/EmbarkStudios/rust-gpu) would like to support `asm!` for our SPIR-V backend. However, we cannot do so purely without frontend support: [this match](d4ea0b3e46/compiler/rustc_target/src/asm/mod.rs (L185)) fails and so `asm!` is not supported ([error reported here](d4ea0b3e46/compiler/rustc_ast_lowering/src/expr.rs (L1095))). To resolve this, we need to stub out register information for SPIR-V to support getting the `asm!` content all the way to [`AsmBuilderMethods::codegen_inline_asm`](https://doc.rust-lang.org/nightly/nightly-rustc/rustc_codegen_ssa/traits/trait.AsmBuilderMethods.html#tymethod.codegen_inline_asm), at which point the rust-gpu backend can do all the parsing and codegen that is needed.

This is a pretty weird PR - adding support for a backend that isn't in-tree feels pretty gross to me, but I don't see an easy way around this. ``@Amanieu`` said I should submit it anyway, so, here we are! Let me know if this needs to go through a more formal process (MCP?) and what I should do to help this along.

I based this off the [wasm asm PR](https://github.com/rust-lang/rust/pull/78684), which unfortunately this PR conflicts with that one quite a bit, sorry for any merge conflict pain :(

---

Some open questions:

- What do we call the register class? Some context, SPIR-V is an SSA-based IR, there are "instructions" that create IDs (referred to as `<id>` in the spec), which can be referenced by other instructions. So, `reg` isn't exactly accurate, they're SSA IDs, not re-assignable registers.
- What happens when a SPIR-V register gets to the LLVM backend? Right now it's a `bug!`, but should that be a `sess.fatal()`? I'm not sure if it's even possible to reach that point, maybe there's a check that prevents the `spirv` target from even reaching that codepath.
2020-11-12 19:46:14 +01:00
khyperia
0e34b73996 Change capitalization of Spirv to SpirV
This matches the capitalization of RiscV
2020-11-11 19:18:06 +01:00
khyperia
f3441348e0 Add asm register information for SPIR-V 2020-11-11 17:38:02 +01:00
Vadim Petrochenkov
bf66988aa1 Collapse all uses of target.options.foo into target.foo
with an eye on merging `TargetOptions` into `Target`.

`TargetOptions` as a separate structure is mostly an implementation detail of `Target` construction, all its fields logically belong to `Target` and available from `Target` through `Deref` impls.
2020-11-08 17:29:13 +03:00
Joshua Nelson
57c6ed0c07 Fix even more clippy warnings 2020-10-30 10:13:39 -04:00
Lzu Tao
4d570fb45e Removes reg aliases since there are many ABIs: o32/n32/n64 2020-10-04 12:01:21 +00:00
Lzu Tao
79f477bb1f Add asm! support for mips64 2020-10-04 12:01:21 +00:00
Lzu Tao
6cb062dacf mips32: Add f64 hard-float support
co-authored-by: Amanieu <amanieu@gmail.com>
2020-10-04 03:35:52 +00:00
Lzu Tao
9000710959 Add MIPS asm! support
This patch also:
* Add soft-float supports: only f32
* zero-extend i8/i16 to i32 because MIPS only supports register-length
  arithmetic.
* Update table in asm! chapter in unstable book.
2020-09-27 02:36:50 +00:00
mark
9e5f7d5631 mv compiler to compiler/ 2020-08-30 18:45:07 +03:00