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23 Commits

Author SHA1 Message Date
Jacob Pratt
49c82f31a8
Remove crate visibility usage in compiler 2022-05-20 20:04:54 -04:00
Amanieu d'Antras
dc345d8bff Reimplement lowering of sym operands for asm! so that it also works with global_asm! 2022-04-14 15:32:03 +01:00
Amanieu d'Antras
fc41d4bf35 Take CodegenFnAttrs into account when validating asm! register operands 
Checking of asm! register operands now properly takes function
attributes such as #[target_feature] and #[instruction_set] into
account.
 2022-02-21 18:28:22 +00:00
Amanieu d'Antras
1ceb104851 On ARM, use relocation_model to detect whether r9 should be reserved 
The previous approach of checking for the reserve-r9 target feature
didn't actually work because LLVM only sets this feature very late when
initializing the per-function subtarget.
 2022-02-21 18:28:22 +00:00
Matthias Krüger
f2d6770f77
Rollup merge of #94146 - est31:let_else, r=cjgillot 
Adopt let else in more places

Continuation of #89933, #91018, #91481, #93046, #93590, #94011.

I have extended my clippy lint to also recognize tuple passing and match statements. The diff caused by fixing it is way above 1 thousand lines. Thus, I split it up into multiple pull requests to make reviewing easier. This is the biggest of these PRs and handles the changes outside of rustdoc, rustc_typeck, rustc_const_eval, rustc_trait_selection, which were handled in PRs #94139, #94142, #94143, #94144.
 2022-02-20 00:37:34 +01:00
est31
2ef8af6619 Adopt let else in more places 2022-02-19 17:27:43 +01:00
Amanieu d'Antras
11250b8661 asm: Allow the use of r8-r14 as clobbers on Thumb1 
Previously these were entirely disallowed, except for r11 which was
allowed by accident.
 2022-02-18 20:26:40 +00:00
Amanieu d'Antras
20e6c1d013 Fix incorrect register conflict detection in asm! 
This would previously incorrectly reject two subregisters that were
distinct but part of the same larger register, for example `al` and
`ah`.
 2022-02-10 18:04:09 +00:00
bjorn3
042aa379a5 Pass target_features set instead of has_feature closure 
This avoids unnecessary monomorphizations in codegen backends
 2022-01-17 18:06:30 +01:00
bjorn3
991cbd1503 Use Symbol for target features in asm handling 
This saves a couple of Symbol::intern calls
 2022-01-17 18:06:27 +01:00
Amanieu d'Antras
8716f2780e asm: Allow using r9 (ARM) and x18 (AArch64) if they are not reserved by 
the current target.
 2021-12-10 00:51:39 +00:00
cynecx
686ace3b41 add unwind_asm feature gate for may_unwind option 2021-12-03 23:51:49 +01:00
asquared31415
b233d3b5da Add support for specifying multiple clobber_abi in asm! 
Allow multiple clobber_abi in asm

Update docs
Fix aarch64 test
Combine abis
Emit duplicate ABI error, empty ABI list error
multiple clobber_abi
 2021-11-10 01:06:03 -05:00
Amanieu d'Antras
eb32c00216 Add features gates for experimental asm features 2021-11-07 01:23:53 +00:00
Yuki Okushi
630df7c54a
Remove unnecessary check for registers 
`is_clobber()` already checks if `reg` is a register and the both
values should be the same.
 2021-10-26 11:02:51 +09:00
Yuki Okushi
f5cbb9b9e6
Fix some typos 2021-10-26 11:02:47 +09:00
asquared31415
271da7d8bc make #[target_feature] work with asm register classes 2021-10-07 15:42:18 -04:00
Vadim Petrochenkov
59013cdebe ast_lowering: Introduce lower_span for catching all spans entering HIR 2021-08-29 10:49:40 +03:00
asquared31415
0b81c2eb82 Move named_asm_labels to a HIR lint 2021-08-24 08:23:58 -04:00
Amanieu d'Antras
3fd463a5ca Add support for clobber_abi to asm! 2021-08-12 12:43:11 +01:00
Amanieu d'Antras
e1c3f5e017 Add clobber-only register classes for asm! 
These are needed to properly express a function call ABI using a clobber
list, even though we don't support passing actual values into/out of
these registers.
 2021-07-10 17:29:00 +02:00
Amanieu d'Antras
bb6bec1d55 Clarify error message when both asm! and global_asm! are unsupported 2021-05-13 22:31:58 +01:00
Amanieu d'Antras
5918ee4317 Add support for const operands and options to global_asm! 
On x86, the default syntax is also switched to Intel to match asm!
 2021-05-13 22:31:57 +01:00