Commit Graph

15 Commits

Author SHA1 Message Date
Urgau
19e11760ab Update rustc_codegen_gcc libc 2023-12-07 14:59:37 +01:00
Antoni Boucher
75fce09751 Merge commit '2e8386e9fb3506cef991d04f8b3bc78f9a0c2630' into subtree-update_cg_gcc_2023-11-17 2023-11-19 13:42:13 -05:00
Antoni Boucher
9f4f90b19a Merge commit 'e4fe941b11a55c5005630696e9b6d81c65f7bd04' into subtree-update_cg_gcc_2023-10-25 2023-10-26 17:42:02 -04:00
Antoni Boucher
242a482c88 Merge commit '11a0cceab966e5ff1058ddbcab5977e8a1d6d290' into subtree-update_cg_gcc_2023-10-09 2023-10-09 15:53:34 -04:00
Antoni Boucher
3dd0699e45 Update Cargo.lock 2023-06-19 20:44:01 -04:00
Ulrich Weigand
2bfd89d91b Update gccjit and remove libc 0.1 dependency 2023-03-30 18:30:56 +02:00
Antoni Boucher
94538736a8 Update gccjit 2023-03-05 12:16:33 -05:00
Antoni Boucher
d725cfb6ab Merge commit '08a6d6e16b5efe217123e780398969946266268f' into sync-cg_gcc-2023-03-04 2023-03-05 12:03:19 -05:00
bjorn3
690085c2da Rewrite LLVM's archive writer in Rust
This allows it to be used by other codegen backends
2022-11-26 19:35:32 +00:00
Antoni Boucher
fac57d9a06 Merge commit 'e8dca3e87d164d2806098c462c6ce41301341f68' into sync_from_cg_gcc 2022-06-06 22:04:37 -04:00
bjorn3
3888aafe3a Merge commit '39683d8eb7a32a74bea96ecbf1e87675d3338506' into sync_cg_gcc-2022-03-26 2022-03-26 18:29:37 +01:00
bjorn3
54d2ec1a82 Merge commit '1411a98352ba6bee8ba3b0131c9243e5db1e6a2e' into sync_cg_clif-2021-12-31 2021-12-31 16:26:32 +01:00
antoyo
64c561dc22
Fix global initialization (#91)
* Make define_global() return a RValue directly
* Return LValue in functions declaring a global variable
* Remove useless cast
* Fix bytes_in_context to use an array rvalue
* Remove global_names which is unused
* Make const_struct create a constant struct
* Correctly initialize global in static_addr_of_mut
* Fix global variable initialization
* Remove workaround for ARGV
2021-09-26 12:20:02 -04:00
Commeownist
7c707e4b95
Implement basic inline asm support (#72)
* Implement basic support for inline assembly

* Disable LTO

We don't support it yet at all

* Handle `inout(reg) var` correctly

Turns out that `+` readwrite output registers cannot be tied with
input variables.

* Add limited support for llvm_asm!

* Handle CHANNEL correctly

* Add support for arbitrary explicit registers

* Handle symbols properly

* Add rudimentary asm tests

* Exclude llvm_asm! tests from tests runs

* Insert `__builtin_unreachable()` after diverging asm blocks
2021-09-05 11:26:01 -04:00
Antoni Boucher
afae271d5d Initial commit 2021-08-12 21:46:50 -04:00