`Conf` macro improvements
changelog: Allow `default_trait_access` in macros
Mainly this is a change to use serde as in [Manually implementing Deserialize for a struct](https://serde.rs/deserialize-struct.html), which opens the door for a cleaner implementation overall.
* Allow `default_trait_access` in macros (tangential, but used in this PR)
* Deserialize into `TryConf { conf, errors }` instead of using a global `ERRORS` variable.
* Improve the `define_Conf!` macro
* Remove the redundant string literal `(name, "name", ..)`
* Support deprecated configs with `#[conf_deprecated(message)]`. Message shows in error.
* Make the default value optional. Use `Default::default()` if omitted.
* Invalid config value error now shows the key (see test output)
* Cleaner `impl Default for Conf` (no `toml::from_str("")`)
Remove dead code in `rustc_session::Options`
- Don't recompile the same functions for each debugging option
This reduces the amount of items in the crate by quite a lot.
- Remove unused `parse_opt_list` and `parse_pathbuf_push` functions
- Remove unused macro parameters
- Remove `allow(dead_code)`.
Don't download cargo twice when download-rustc is set
Previously, this caused a bug on NixOS:
1. bootstrap.py would download and patch stage0/cargo
2. bootstrap.py would download nightly cargo, but extract it to
stage0/cargo instead of ci-rustc/cargo. It would still try (and fail) to patch ci-rustc/cargo.
3. bootstrap.py would fail to build rustbuild because stage0/cargo
wasn't patched.
The "proper" fix is to extract nightly cargo to ci-rustc instead, but it
doesn't seem to be necessary at all, so this just skips downloading it
instead.
Fixes https://github.com/rust-lang/rust/issues/84702
[Arm64] use isb instruction instead of yield in spin loops
On arm64 we have seen on several databases that ISB (instruction synchronization
barrier) is better to use than yield in a spin loop. The yield instruction is a
nop. The isb instruction puts the processor to sleep for some short time. isb
is a good equivalent to the pause instruction on x86.
Below is an experiment that shows the effects of yield and isb on Arm64 and the
time of a pause instruction on x86 Intel processors. The micro-benchmarks use
https://github.com/google/benchmark.git
```
$ cat a.cc
static void BM_scalar_increment(benchmark::State& state) {
int i = 0;
for (auto _ : state)
benchmark::DoNotOptimize(i++);
}
BENCHMARK(BM_scalar_increment);
static void BM_yield(benchmark::State& state) {
for (auto _ : state)
asm volatile("yield"::);
}
BENCHMARK(BM_yield);
static void BM_isb(benchmark::State& state) {
for (auto _ : state)
asm volatile("isb"::);
}
BENCHMARK(BM_isb);
BENCHMARK_MAIN();
$ g++ -o run a.cc -O2 -lbenchmark -lpthread
$ ./run
--------------------------------------------------------------
Benchmark Time CPU Iterations
--------------------------------------------------------------
AWS Graviton2 (Neoverse-N1) processor:
BM_scalar_increment 0.485 ns 0.485 ns 1000000000
BM_yield 0.400 ns 0.400 ns 1000000000
BM_isb 13.2 ns 13.2 ns 52993304
AWS Graviton (A-72) processor:
BM_scalar_increment 0.897 ns 0.874 ns 801558633
BM_yield 0.877 ns 0.875 ns 800002377
BM_isb 13.0 ns 12.7 ns 55169412
Apple Arm64 M1 processor:
BM_scalar_increment 0.315 ns 0.315 ns 1000000000
BM_yield 0.313 ns 0.313 ns 1000000000
BM_isb 9.06 ns 9.06 ns 77259282
```
```
static void BM_pause(benchmark::State& state) {
for (auto _ : state)
asm volatile("pause"::);
}
BENCHMARK(BM_pause);
Intel Skylake processor:
BM_scalar_increment 0.295 ns 0.295 ns 1000000000
BM_pause 41.7 ns 41.7 ns 16780553
```
Tested on Graviton2 aarch64-linux with `./x.py test`.
Allow running `x.py test --stage 2 src/tools/linkchecker` with `download-rustc = true`
Previously, the LD_LIBRARY_PATH for the linkchecker looked like
`build/x86_64-unknown-linux-gnu/stage1/lib/rustlib/x86_64-unknown-linux-gnu/lib`, because the linkchecker depends on the master copy of the standard library. This is true, but doesn't include the library path for the compiler libraries:
```
/home/joshua/src/rust/rust/build/x86_64-unknown-linux-gnu/stage1-tools-bin/error_index_generator: error while loading shared libraries: libLLVM-12-rust-1.53.0-nightly.so: cannot open shared object file: No such file or directory
```
That file is in
`build/x86_64-unknown-linux-gnu/stage1/lib/libLLVM-12-rust-1.53.0-nightly.so`,
which wasn't included in the dynamic path. This adds `build/x86_64-unknown-linux-gnu/stage1/lib` to the dynamic path for the linkchecker.
Fixes: #84018
With `-Z instrument-coverage`, coverage reporting of dead blocks
(for example, blocks dropped because a conditional branch is dropped,
based on const evaluation) is now supported.
If `instrument-coverage` is enabled, `simplify::remove_dead_blocks()`
finds all dropped coverage `Statement`s and adds their `code_region`s as
`Unreachable` coverage `Statement`s to the `START_BLOCK`, so they are
still included in the coverage map.
Check out the resulting changes in the test coverage reports in this PR.
This ensures that `ParamEnv::and` preserves the original `caller_bounds`
when we have a value containing fresh tys/consts. This ensures that when
we cache a `SelectionCandidate`, the cache key (a `ParamEnvAnd`)
contains all of the information that influenced the computation of our
result (e.g. we may end up choosing a `ParamCandidate`)
Move HIR parenting information out of hir_owner
Split out of #82681.
The parent of a HIR node and its content are currently bundled together, but are rarely used together.
This PR separates both information in two distinct queries for HIR owners.
This reduces incremental invalidation for HIR items that appear within a function body when this body (and the local ids) changes.
added --no-run option for rustdoc
resolve#59053
add `--no-run` option for `rustdoc` for compiling doc test but not running them.
Intended for use with `--persist-doctests`.
Be stricter about rejecting LLVM reserved registers in asm!
LLVM will silently produce incorrect code if these registers are used as operands.
cc `@rust-lang/wg-inline-asm`
Rollup of 8 pull requests
Successful merges:
- #84601 (rustdoc: Only store locations in Cache::extern_locations and calculate the other info on-demand)
- #84704 (platform-support.md: Update for consistency with Target Tier Policy)
- #84724 (Replace llvm::sys::fs::F_None with llvm::sys::fs::OF_None)
- #84740 (Reset the docs' copy path button after 1 second)
- #84749 (Sync `rustc_codegen_cranelift`)
- #84756 (Add a ToC to the Target Tier Policy documentation)
- #84765 (Update cargo)
- #84774 (Fix misspelling)
Failed merges:
r? `@ghost`
`@rustbot` modify labels: rollup
Add a ToC to the Target Tier Policy documentation
The policy document is quite lengthy, I figured it might be good to have a quick way to jump to the specific tier policies.
Sync `rustc_codegen_cranelift`
Retrying #84746
r? ``@bjorn3``
---
Edit(bjorn3): Since the last sync there have been some refactorings around the driver code in preparation for a planned new feature. In addition ``@mominul`` implemented `-Ctarget-cpu` support and ``@XAMPPRocky`` fixed compilation of cg_clif itself for Windows with the MSVC toolchain.
