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Rollup merge of #119738 - esp-rs:esp32p4-espidf, r=Nilstrieb

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Add `riscv32imafc-esp-espidf` tier 3 target for the ESP32-P4.

The tier 3 target answers in the original PR are still relevant, so please review them here: https://github.com/rust-lang/rust/pull/87666#issue-957268176

cc: ``@ivmarkov``
This commit is contained in:
Matthias Krüger 2024-01-09 00:19:36 +01:00 committed by GitHub
commit eb6ce92473
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4 changed files with 34 additions and 0 deletions
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2
compiler/rustc_target/src/spec/mod.rs
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@ -1601,6 +1601,8 @@ supported_targets! {
("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),
("riscv32imc-esp-espidf", riscv32imc_esp_espidf),
("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
("riscv32imafc-esp-espidf", riscv32imafc_esp_espidf),
("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
("riscv32imafc-unknown-none-elf", riscv32imafc_unknown_none_elf),
("riscv32imac-unknown-xous-elf", riscv32imac_unknown_xous_elf),

30
compiler/rustc_target/src/spec/targets/riscv32imafc_esp_espidf.rs Normal file
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@ -0,0 +1,30 @@
use crate::spec::{cvs, PanicStrategy, RelocModel, Target, TargetOptions};
pub fn target() -> Target {
Target {
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
llvm_target: "riscv32".into(),
pointer_width: 32,
arch: "riscv32".into(),
options: TargetOptions {
families: cvs!["unix"],
os: "espidf".into(),
env: "newlib".into(),
vendor: "espressif".into(),
linker: Some("riscv32-esp-elf-gcc".into()),
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
atomic_cas: true,
llvm_abiname: "ilp32f".into(),
features: "+m,+a,+c,+f".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}

1
src/doc/rustc/src/platform-support.md
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@ -323,6 +323,7 @@ target | std | host | notes
[`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? | | RISC-V Xous (RV32IMAC ISA)
[`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
[`riscv32imac-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
[`riscv32imafc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
[`riscv64gc-unknown-hermit`](platform-support/hermit.md) | ✓ | | RISC-V Hermit
`riscv64gc-unknown-freebsd` | | | RISC-V FreeBSD
`riscv64gc-unknown-fuchsia` | | | RISC-V Fuchsia

1
src/doc/rustc/src/platform-support/esp-idf.md
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@ -19,6 +19,7 @@ The target names follow this format: `$ARCH-esp-espidf`, where `$ARCH` specifies
| `riscv32imc-esp-espidf` | [ESP32-C3](https://www.espressif.com/en/products/socs/esp32-c3) | `v4.3` |
| `riscv32imac-esp-espidf` | [ESP32-C6](https://www.espressif.com/en/products/socs/esp32-c6) | `v5.1` |
| `riscv32imac-esp-espidf` | [ESP32-H2](https://www.espressif.com/en/products/socs/esp32-h2) | `v5.1` |
| `riscv32imafc-esp-espidf`| [ESP32-P4](https://www.espressif.com/en/news/ESP32-P4) | `v5.2` |
It is recommended to use the latest ESP-IDF stable release if possible.