Auto merge of #120055 - nikic:llvm-18, r=cuviper
Update to LLVM 18 LLVM 18 final is planned to be released on Mar 5th. Rust 1.78 is planned to be released on May 2nd. Tested images: dist-x86_64-linux, dist-s390x-linux, dist-aarch64-linux, dist-riscv64-linux, dist-loongarch64-linux, dist-x86_64-freebsd, dist-x86_64-illumos, dist-x86_64-musl, x86_64-linux-integration, test-various, armhf-gnu, i686-msvc, x86_64-msvc, i686-mingw, x86_64-mingw, x86_64-apple-1, x86_64-apple-2, dist-aarch64-apple r? `@ghost`
This commit is contained in:
commit
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@ -33,7 +33,7 @@
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[submodule "src/llvm-project"]
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[submodule "src/llvm-project"]
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path = src/llvm-project
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path = src/llvm-project
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url = https://github.com/rust-lang/llvm-project.git
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url = https://github.com/rust-lang/llvm-project.git
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branch = rustc/17.0-2023-12-14
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branch = rustc/18.0-2024-02-13
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shallow = true
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shallow = true
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[submodule "src/doc/embedded-book"]
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[submodule "src/doc/embedded-book"]
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path = src/doc/embedded-book
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path = src/doc/embedded-book
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@ -747,9 +747,9 @@ checksum = "55b672471b4e9f9e95499ea597ff64941a309b2cdbffcc46f2cc5e2d971fd335"
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[[package]]
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[[package]]
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name = "compiler_builtins"
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name = "compiler_builtins"
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version = "0.1.105"
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version = "0.1.108"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "3686cc48897ce1950aa70fd595bd2dc9f767a3c4cca4cd17b2cb52a2d37e6eb4"
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checksum = "d68bc55329711cd719c2687bb147bc06211b0521f97ef398280108ccb23227e9"
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dependencies = [
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dependencies = [
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"cc",
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"cc",
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"rustc-std-workspace-core",
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"rustc-std-workspace-core",
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@ -371,10 +371,10 @@ extern "C" void LLVMRustPrintTargetCPUs(LLVMTargetMachineRef TM,
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}
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}
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extern "C" size_t LLVMRustGetTargetFeaturesCount(LLVMTargetMachineRef TM) {
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extern "C" size_t LLVMRustGetTargetFeaturesCount(LLVMTargetMachineRef TM) {
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#ifdef LLVM_RUSTLLVM
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#if LLVM_VERSION_GE(18, 0)
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const TargetMachine *Target = unwrap(TM);
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const TargetMachine *Target = unwrap(TM);
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const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo();
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const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo();
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const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getFeatureTable();
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const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getAllProcessorFeatures();
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return FeatTable.size();
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return FeatTable.size();
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#else
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#else
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return 0;
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return 0;
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@ -383,10 +383,10 @@ extern "C" size_t LLVMRustGetTargetFeaturesCount(LLVMTargetMachineRef TM) {
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extern "C" void LLVMRustGetTargetFeature(LLVMTargetMachineRef TM, size_t Index,
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extern "C" void LLVMRustGetTargetFeature(LLVMTargetMachineRef TM, size_t Index,
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const char** Feature, const char** Desc) {
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const char** Feature, const char** Desc) {
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#ifdef LLVM_RUSTLLVM
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#if LLVM_VERSION_GE(18, 0)
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const TargetMachine *Target = unwrap(TM);
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const TargetMachine *Target = unwrap(TM);
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const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo();
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const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo();
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const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getFeatureTable();
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const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getAllProcessorFeatures();
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const SubtargetFeatureKV Feat = FeatTable[Index];
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const SubtargetFeatureKV Feat = FeatTable[Index];
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*Feature = Feat.Key;
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*Feature = Feat.Key;
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*Desc = Feat.Desc;
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*Desc = Feat.Desc;
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@ -412,9 +412,7 @@ fn run(self, builder: &Builder<'_>) -> LlvmResult {
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}
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}
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if target.is_msvc() {
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if target.is_msvc() {
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cfg.define("LLVM_USE_CRT_DEBUG", "MT");
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cfg.define("CMAKE_MSVC_RUNTIME_LIBRARY", "MultiThreaded");
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cfg.define("LLVM_USE_CRT_RELEASE", "MT");
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cfg.define("LLVM_USE_CRT_RELWITHDEBINFO", "MT");
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cfg.static_crt(true);
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cfg.static_crt(true);
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}
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}
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@ -134,6 +134,8 @@ ENV CFLAGS_armv5te_unknown_linux_musleabi="-march=armv5te -marm -mfloat-abi=soft
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CFLAGS_riscv32imc_unknown_none_elf=-march=rv32imc -mabi=ilp32 \
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CFLAGS_riscv32imc_unknown_none_elf=-march=rv32imc -mabi=ilp32 \
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CC_riscv32imac_unknown_none_elf=riscv32-unknown-elf-gcc \
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CC_riscv32imac_unknown_none_elf=riscv32-unknown-elf-gcc \
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CFLAGS_riscv32imac_unknown_none_elf=-march=rv32imac -mabi=ilp32 \
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CFLAGS_riscv32imac_unknown_none_elf=-march=rv32imac -mabi=ilp32 \
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CC_riscv32imafc_unknown_none_elf=riscv32-unknown-elf-gcc \
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CFLAGS_riscv32imafc_unknown_none_elf=-march=rv32imafc -mabi=ilp32 \
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CC_riscv64imac_unknown_none_elf=riscv64-unknown-elf-gcc \
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CC_riscv64imac_unknown_none_elf=riscv64-unknown-elf-gcc \
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CFLAGS_riscv64imac_unknown_none_elf=-march=rv64imac -mabi=lp64 \
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CFLAGS_riscv64imac_unknown_none_elf=-march=rv64imac -mabi=lp64 \
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CC_riscv64gc_unknown_none_elf=riscv64-unknown-elf-gcc \
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CC_riscv64gc_unknown_none_elf=riscv64-unknown-elf-gcc \
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@ -59,6 +59,7 @@ ENV WASM_SCRIPT python3 /checkout/x.py --stage 2 test --host='' --target $WASM_T
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tests/codegen \
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tests/codegen \
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tests/assembly \
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tests/assembly \
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library/core
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library/core
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ENV CC_wasm32_unknown_unknown=clang-11
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ENV NVPTX_TARGETS=nvptx64-nvidia-cuda
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ENV NVPTX_TARGETS=nvptx64-nvidia-cuda
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ENV NVPTX_SCRIPT python3 /checkout/x.py --stage 2 test --host='' --target $NVPTX_TARGETS \
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ENV NVPTX_SCRIPT python3 /checkout/x.py --stage 2 test --host='' --target $NVPTX_TARGETS \
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@ -3,6 +3,7 @@ FROM ubuntu:22.04
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ARG DEBIAN_FRONTEND=noninteractive
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ARG DEBIAN_FRONTEND=noninteractive
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RUN apt-get update && apt-get install -y --no-install-recommends \
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RUN apt-get update && apt-get install -y --no-install-recommends \
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build-essential \
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build-essential \
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clang-15 \
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g++ \
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g++ \
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make \
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make \
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ninja-build \
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ninja-build \
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@ -46,6 +47,9 @@ ENV TARGETS=x86_64-fuchsia
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ENV TARGETS=$TARGETS,x86_64-unknown-linux-gnu
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ENV TARGETS=$TARGETS,x86_64-unknown-linux-gnu
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ENV TARGETS=$TARGETS,wasm32-unknown-unknown
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ENV TARGETS=$TARGETS,wasm32-unknown-unknown
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# Fuchsia clang does not have wasm target enabled, use system clang.
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ENV CC_wasm32_unknown_unknown=clang-15
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COPY scripts/sccache.sh /scripts/
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COPY scripts/sccache.sh /scripts/
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RUN sh /scripts/sccache.sh
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RUN sh /scripts/sccache.sh
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@ -1 +1 @@
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Subproject commit 700fbf978e6c5bb297d12963206f7487722de480
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Subproject commit 9ea7f739f257b049a65deeb1f2455bb2ea021cfa
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@ -47,7 +47,7 @@ pub fn iter_repeat_n_next(it: &mut std::iter::RepeatN<NotCopy>) -> Option<NotCop
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#[no_mangle]
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#[no_mangle]
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// CHECK-LABEL: @vec_extend_via_iter_repeat_n
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// CHECK-LABEL: @vec_extend_via_iter_repeat_n
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pub fn vec_extend_via_iter_repeat_n() -> Vec<u8> {
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pub fn vec_extend_via_iter_repeat_n() -> Vec<u8> {
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// CHECK: %[[ADDR:.+]] = tail call noundef dereferenceable_or_null(1234) ptr @__rust_alloc(i64 noundef 1234, i64 noundef 1)
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// CHECK: %[[ADDR:.+]] = tail call {{(noalias )?}}noundef dereferenceable_or_null(1234) ptr @__rust_alloc(i64 noundef 1234, i64 noundef 1)
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// CHECK: tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(1234) %[[ADDR]], i8 42, i64 1234,
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// CHECK: tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(1234) %[[ADDR]], i8 42, i64 1234,
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let n = 1234_usize;
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let n = 1234_usize;
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