Auto merge of #120055 - nikic:llvm-18, r=cuviper

Update to LLVM 18

LLVM 18 final is planned to be released on Mar 5th. Rust 1.78 is planned to be released on May 2nd.

Tested images: dist-x86_64-linux, dist-s390x-linux, dist-aarch64-linux, dist-riscv64-linux, dist-loongarch64-linux, dist-x86_64-freebsd, dist-x86_64-illumos, dist-x86_64-musl, x86_64-linux-integration, test-various, armhf-gnu, i686-msvc, x86_64-msvc, i686-mingw, x86_64-mingw, x86_64-apple-1, x86_64-apple-2, dist-aarch64-apple

r? `@ghost`
This commit is contained in:
bors 2024-02-13 15:07:28 +00:00
commit eaff1af8fd
9 changed files with 17 additions and 12 deletions

2
.gitmodules vendored
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@ -33,7 +33,7 @@
[submodule "src/llvm-project"] [submodule "src/llvm-project"]
path = src/llvm-project path = src/llvm-project
url = https://github.com/rust-lang/llvm-project.git url = https://github.com/rust-lang/llvm-project.git
branch = rustc/17.0-2023-12-14 branch = rustc/18.0-2024-02-13
shallow = true shallow = true
[submodule "src/doc/embedded-book"] [submodule "src/doc/embedded-book"]
path = src/doc/embedded-book path = src/doc/embedded-book

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@ -747,9 +747,9 @@ checksum = "55b672471b4e9f9e95499ea597ff64941a309b2cdbffcc46f2cc5e2d971fd335"
[[package]] [[package]]
name = "compiler_builtins" name = "compiler_builtins"
version = "0.1.105" version = "0.1.108"
source = "registry+https://github.com/rust-lang/crates.io-index" source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3686cc48897ce1950aa70fd595bd2dc9f767a3c4cca4cd17b2cb52a2d37e6eb4" checksum = "d68bc55329711cd719c2687bb147bc06211b0521f97ef398280108ccb23227e9"
dependencies = [ dependencies = [
"cc", "cc",
"rustc-std-workspace-core", "rustc-std-workspace-core",

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@ -371,10 +371,10 @@ extern "C" void LLVMRustPrintTargetCPUs(LLVMTargetMachineRef TM,
} }
extern "C" size_t LLVMRustGetTargetFeaturesCount(LLVMTargetMachineRef TM) { extern "C" size_t LLVMRustGetTargetFeaturesCount(LLVMTargetMachineRef TM) {
#ifdef LLVM_RUSTLLVM #if LLVM_VERSION_GE(18, 0)
const TargetMachine *Target = unwrap(TM); const TargetMachine *Target = unwrap(TM);
const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo(); const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo();
const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getFeatureTable(); const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getAllProcessorFeatures();
return FeatTable.size(); return FeatTable.size();
#else #else
return 0; return 0;
@ -383,10 +383,10 @@ extern "C" size_t LLVMRustGetTargetFeaturesCount(LLVMTargetMachineRef TM) {
extern "C" void LLVMRustGetTargetFeature(LLVMTargetMachineRef TM, size_t Index, extern "C" void LLVMRustGetTargetFeature(LLVMTargetMachineRef TM, size_t Index,
const char** Feature, const char** Desc) { const char** Feature, const char** Desc) {
#ifdef LLVM_RUSTLLVM #if LLVM_VERSION_GE(18, 0)
const TargetMachine *Target = unwrap(TM); const TargetMachine *Target = unwrap(TM);
const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo(); const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo();
const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getFeatureTable(); const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getAllProcessorFeatures();
const SubtargetFeatureKV Feat = FeatTable[Index]; const SubtargetFeatureKV Feat = FeatTable[Index];
*Feature = Feat.Key; *Feature = Feat.Key;
*Desc = Feat.Desc; *Desc = Feat.Desc;

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@ -412,9 +412,7 @@ fn run(self, builder: &Builder<'_>) -> LlvmResult {
} }
if target.is_msvc() { if target.is_msvc() {
cfg.define("LLVM_USE_CRT_DEBUG", "MT"); cfg.define("CMAKE_MSVC_RUNTIME_LIBRARY", "MultiThreaded");
cfg.define("LLVM_USE_CRT_RELEASE", "MT");
cfg.define("LLVM_USE_CRT_RELWITHDEBINFO", "MT");
cfg.static_crt(true); cfg.static_crt(true);
} }

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@ -134,6 +134,8 @@ ENV CFLAGS_armv5te_unknown_linux_musleabi="-march=armv5te -marm -mfloat-abi=soft
CFLAGS_riscv32imc_unknown_none_elf=-march=rv32imc -mabi=ilp32 \ CFLAGS_riscv32imc_unknown_none_elf=-march=rv32imc -mabi=ilp32 \
CC_riscv32imac_unknown_none_elf=riscv32-unknown-elf-gcc \ CC_riscv32imac_unknown_none_elf=riscv32-unknown-elf-gcc \
CFLAGS_riscv32imac_unknown_none_elf=-march=rv32imac -mabi=ilp32 \ CFLAGS_riscv32imac_unknown_none_elf=-march=rv32imac -mabi=ilp32 \
CC_riscv32imafc_unknown_none_elf=riscv32-unknown-elf-gcc \
CFLAGS_riscv32imafc_unknown_none_elf=-march=rv32imafc -mabi=ilp32 \
CC_riscv64imac_unknown_none_elf=riscv64-unknown-elf-gcc \ CC_riscv64imac_unknown_none_elf=riscv64-unknown-elf-gcc \
CFLAGS_riscv64imac_unknown_none_elf=-march=rv64imac -mabi=lp64 \ CFLAGS_riscv64imac_unknown_none_elf=-march=rv64imac -mabi=lp64 \
CC_riscv64gc_unknown_none_elf=riscv64-unknown-elf-gcc \ CC_riscv64gc_unknown_none_elf=riscv64-unknown-elf-gcc \

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@ -59,6 +59,7 @@ ENV WASM_SCRIPT python3 /checkout/x.py --stage 2 test --host='' --target $WASM_T
tests/codegen \ tests/codegen \
tests/assembly \ tests/assembly \
library/core library/core
ENV CC_wasm32_unknown_unknown=clang-11
ENV NVPTX_TARGETS=nvptx64-nvidia-cuda ENV NVPTX_TARGETS=nvptx64-nvidia-cuda
ENV NVPTX_SCRIPT python3 /checkout/x.py --stage 2 test --host='' --target $NVPTX_TARGETS \ ENV NVPTX_SCRIPT python3 /checkout/x.py --stage 2 test --host='' --target $NVPTX_TARGETS \

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@ -3,6 +3,7 @@ FROM ubuntu:22.04
ARG DEBIAN_FRONTEND=noninteractive ARG DEBIAN_FRONTEND=noninteractive
RUN apt-get update && apt-get install -y --no-install-recommends \ RUN apt-get update && apt-get install -y --no-install-recommends \
build-essential \ build-essential \
clang-15 \
g++ \ g++ \
make \ make \
ninja-build \ ninja-build \
@ -46,6 +47,9 @@ ENV TARGETS=x86_64-fuchsia
ENV TARGETS=$TARGETS,x86_64-unknown-linux-gnu ENV TARGETS=$TARGETS,x86_64-unknown-linux-gnu
ENV TARGETS=$TARGETS,wasm32-unknown-unknown ENV TARGETS=$TARGETS,wasm32-unknown-unknown
# Fuchsia clang does not have wasm target enabled, use system clang.
ENV CC_wasm32_unknown_unknown=clang-15
COPY scripts/sccache.sh /scripts/ COPY scripts/sccache.sh /scripts/
RUN sh /scripts/sccache.sh RUN sh /scripts/sccache.sh

@ -1 +1 @@
Subproject commit 700fbf978e6c5bb297d12963206f7487722de480 Subproject commit 9ea7f739f257b049a65deeb1f2455bb2ea021cfa

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@ -47,7 +47,7 @@ pub fn iter_repeat_n_next(it: &mut std::iter::RepeatN<NotCopy>) -> Option<NotCop
#[no_mangle] #[no_mangle]
// CHECK-LABEL: @vec_extend_via_iter_repeat_n // CHECK-LABEL: @vec_extend_via_iter_repeat_n
pub fn vec_extend_via_iter_repeat_n() -> Vec<u8> { pub fn vec_extend_via_iter_repeat_n() -> Vec<u8> {
// CHECK: %[[ADDR:.+]] = tail call noundef dereferenceable_or_null(1234) ptr @__rust_alloc(i64 noundef 1234, i64 noundef 1) // CHECK: %[[ADDR:.+]] = tail call {{(noalias )?}}noundef dereferenceable_or_null(1234) ptr @__rust_alloc(i64 noundef 1234, i64 noundef 1)
// CHECK: tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(1234) %[[ADDR]], i8 42, i64 1234, // CHECK: tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(1234) %[[ADDR]], i8 42, i64 1234,
let n = 1234_usize; let n = 1234_usize;