From a47b9fd2e6738b4256b462380504c77f0752e0b7 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Thu, 5 Oct 2023 18:55:18 +0000 Subject: [PATCH 1/3] Remove stub support for 32bit inline assembly Cranelift doesn't support any 32bit target yet and this helps with keeping everything in sync. --- src/inline_asm.rs | 44 ++------------------------------------------ 1 file changed, 2 insertions(+), 42 deletions(-) diff --git a/src/inline_asm.rs b/src/inline_asm.rs index c9a4a2d3cca..15b9f7ff77b 100644 --- a/src/inline_asm.rs +++ b/src/inline_asm.rs @@ -699,20 +699,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { fn prologue(generated_asm: &mut String, arch: InlineAsmArch) { match arch { - InlineAsmArch::X86 => { - generated_asm.push_str(" push ebp\n"); - generated_asm.push_str(" mov ebp,[esp+8]\n"); - } InlineAsmArch::X86_64 => { generated_asm.push_str(" push rbp\n"); generated_asm.push_str(" mov rbp,rdi\n"); } - InlineAsmArch::RiscV32 => { - generated_asm.push_str(" addi sp, sp, -8\n"); - generated_asm.push_str(" sw ra, 4(sp)\n"); - generated_asm.push_str(" sw s0, 0(sp)\n"); - generated_asm.push_str(" mv s0, a0\n"); - } InlineAsmArch::RiscV64 => { generated_asm.push_str(" addi sp, sp, -16\n"); generated_asm.push_str(" sd ra, 8(sp)\n"); @@ -725,20 +715,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { fn epilogue(generated_asm: &mut String, arch: InlineAsmArch) { match arch { - InlineAsmArch::X86 => { - generated_asm.push_str(" pop ebp\n"); - generated_asm.push_str(" ret\n"); - } InlineAsmArch::X86_64 => { generated_asm.push_str(" pop rbp\n"); generated_asm.push_str(" ret\n"); } - InlineAsmArch::RiscV32 => { - generated_asm.push_str(" lw s0, 0(sp)\n"); - generated_asm.push_str(" lw ra, 4(sp)\n"); - generated_asm.push_str(" addi sp, sp, 8\n"); - generated_asm.push_str(" ret\n"); - } InlineAsmArch::RiscV64 => { generated_asm.push_str(" ld s0, 0(sp)\n"); generated_asm.push_str(" ld ra, 8(sp)\n"); @@ -751,10 +731,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { fn epilogue_noreturn(generated_asm: &mut String, arch: InlineAsmArch) { match arch { - InlineAsmArch::X86 | InlineAsmArch::X86_64 => { + InlineAsmArch::X86_64 => { generated_asm.push_str(" ud2\n"); } - InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => { + InlineAsmArch::RiscV64 => { generated_asm.push_str(" ebreak\n"); } _ => unimplemented!("epilogue_noreturn for {:?}", arch), @@ -768,21 +748,11 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { offset: Size, ) { match arch { - InlineAsmArch::X86 => { - write!(generated_asm, " mov [ebp+0x{:x}], ", offset.bytes()).unwrap(); - reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap(); - generated_asm.push('\n'); - } InlineAsmArch::X86_64 => { write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap(); reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap(); generated_asm.push('\n'); } - InlineAsmArch::RiscV32 => { - generated_asm.push_str(" sw "); - reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap(); - writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap(); - } InlineAsmArch::RiscV64 => { generated_asm.push_str(" sd "); reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap(); @@ -799,21 +769,11 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { offset: Size, ) { match arch { - InlineAsmArch::X86 => { - generated_asm.push_str(" mov "); - reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap(); - writeln!(generated_asm, ", [ebp+0x{:x}]", offset.bytes()).unwrap(); - } InlineAsmArch::X86_64 => { generated_asm.push_str(" mov "); reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap(); writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap(); } - InlineAsmArch::RiscV32 => { - generated_asm.push_str(" lw "); - reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap(); - writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap(); - } InlineAsmArch::RiscV64 => { generated_asm.push_str(" ld "); reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap(); From b1421dea1d9f99220880413767ea45dfe988c83e Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Thu, 5 Oct 2023 19:06:08 +0000 Subject: [PATCH 2/3] Support inline asm on AArch64 Also stop changing the frame pointer on x86_64. This confuses unwinders. --- example/mini_core.rs | 6 ++++++ src/global_asm.rs | 23 +++++++++++++++++------ src/inline_asm.rs | 35 ++++++++++++++++++++++++++++++++--- 3 files changed, 55 insertions(+), 9 deletions(-) diff --git a/example/mini_core.rs b/example/mini_core.rs index 34c7e44b288..934e4b1786f 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -683,6 +683,12 @@ pub macro cfg() { /* compiler built-in */ } +#[rustc_builtin_macro] +#[rustc_macro_transparency = "semitransparent"] +pub macro asm() { + /* compiler built-in */ +} + #[rustc_builtin_macro] #[rustc_macro_transparency = "semitransparent"] pub macro global_asm() { diff --git a/src/global_asm.rs b/src/global_asm.rs index baadd7a9e81..ebd9b728d90 100644 --- a/src/global_asm.rs +++ b/src/global_asm.rs @@ -9,16 +9,22 @@ use std::sync::Arc; use rustc_ast::{InlineAsmOptions, InlineAsmTemplatePiece}; use rustc_hir::{InlineAsmOperand, ItemId}; use rustc_session::config::{OutputFilenames, OutputType}; +use rustc_target::asm::InlineAsmArch; use crate::prelude::*; pub(crate) fn codegen_global_asm_item(tcx: TyCtxt<'_>, global_asm: &mut String, item_id: ItemId) { let item = tcx.hir().item(item_id); if let rustc_hir::ItemKind::GlobalAsm(asm) = item.kind { - if !asm.options.contains(InlineAsmOptions::ATT_SYNTAX) { - global_asm.push_str("\n.intel_syntax noprefix\n"); - } else { - global_asm.push_str("\n.att_syntax\n"); + let is_x86 = + matches!(tcx.sess.asm_arch.unwrap(), InlineAsmArch::X86 | InlineAsmArch::X86_64); + + if is_x86 { + if !asm.options.contains(InlineAsmOptions::ATT_SYNTAX) { + global_asm.push_str("\n.intel_syntax noprefix\n"); + } else { + global_asm.push_str("\n.att_syntax\n"); + } } for piece in asm.template { match *piece { @@ -65,7 +71,11 @@ pub(crate) fn codegen_global_asm_item(tcx: TyCtxt<'_>, global_asm: &mut String, } } } - global_asm.push_str("\n.att_syntax\n\n"); + + global_asm.push('\n'); + if is_x86 { + global_asm.push_str(".att_syntax\n\n"); + } } else { bug!("Expected GlobalAsm found {:?}", item); } @@ -115,11 +125,12 @@ pub(crate) fn compile_global_asm( } // Remove all LLVM style comments - let global_asm = global_asm + let mut global_asm = global_asm .lines() .map(|line| if let Some(index) = line.find("//") { &line[0..index] } else { line }) .collect::>() .join("\n"); + global_asm.push('\n'); let output_object_file = config.output_filenames.temp_path(OutputType::Object, Some(cgu_name)); diff --git a/src/inline_asm.rs b/src/inline_asm.rs index 15b9f7ff77b..402dc457317 100644 --- a/src/inline_asm.rs +++ b/src/inline_asm.rs @@ -701,7 +701,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { match arch { InlineAsmArch::X86_64 => { generated_asm.push_str(" push rbp\n"); - generated_asm.push_str(" mov rbp,rdi\n"); + generated_asm.push_str(" mov rbp,rsp\n"); + generated_asm.push_str(" push rbx\n"); // rbx is callee saved + // rbx is reserved by LLVM for the "base pointer", so rustc doesn't allow using it + generated_asm.push_str(" mov rbx,rdi\n"); } InlineAsmArch::RiscV64 => { generated_asm.push_str(" addi sp, sp, -16\n"); @@ -709,6 +712,13 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { generated_asm.push_str(" sd s0, 0(sp)\n"); generated_asm.push_str(" mv s0, a0\n"); } + InlineAsmArch::AArch64 => { + generated_asm.push_str(" stp fp, lr, [sp, #-32]!\n"); + generated_asm.push_str(" mov fp, sp\n"); + generated_asm.push_str(" str x19, [sp, #24]\n"); // x19 is callee saved + // x19 is reserved by LLVM for the "base pointer", so rustc doesn't allow using it + generated_asm.push_str(" mov x19, x0\n"); + } _ => unimplemented!("prologue for {:?}", arch), } } @@ -716,6 +726,7 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { fn epilogue(generated_asm: &mut String, arch: InlineAsmArch) { match arch { InlineAsmArch::X86_64 => { + generated_asm.push_str(" pop rbx\n"); generated_asm.push_str(" pop rbp\n"); generated_asm.push_str(" ret\n"); } @@ -725,6 +736,11 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { generated_asm.push_str(" addi sp, sp, 16\n"); generated_asm.push_str(" ret\n"); } + InlineAsmArch::AArch64 => { + generated_asm.push_str(" ldr x19, [sp, #24]\n"); + generated_asm.push_str(" ldp fp, lr, [sp], #32\n"); + generated_asm.push_str(" ret\n"); + } _ => unimplemented!("epilogue for {:?}", arch), } } @@ -737,6 +753,9 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { InlineAsmArch::RiscV64 => { generated_asm.push_str(" ebreak\n"); } + InlineAsmArch::AArch64 => { + generated_asm.push_str(" brk #0x1"); + } _ => unimplemented!("epilogue_noreturn for {:?}", arch), } } @@ -749,7 +768,7 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { ) { match arch { InlineAsmArch::X86_64 => { - write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap(); + write!(generated_asm, " mov [rbx+0x{:x}], ", offset.bytes()).unwrap(); reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap(); generated_asm.push('\n'); } @@ -758,6 +777,11 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap(); writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap(); } + InlineAsmArch::AArch64 => { + generated_asm.push_str(" str "); + reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap(); + writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap(); + } _ => unimplemented!("save_register for {:?}", arch), } } @@ -772,13 +796,18 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { InlineAsmArch::X86_64 => { generated_asm.push_str(" mov "); reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap(); - writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap(); + writeln!(generated_asm, ", [rbx+0x{:x}]", offset.bytes()).unwrap(); } InlineAsmArch::RiscV64 => { generated_asm.push_str(" ld "); reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap(); writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap(); } + InlineAsmArch::AArch64 => { + generated_asm.push_str(" ldr "); + reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap(); + writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap(); + } _ => unimplemented!("restore_register for {:?}", arch), } } From 4577c1dc057685f9418c76d1ccfc2de0210bd0e8 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Thu, 5 Oct 2023 19:23:40 +0000 Subject: [PATCH 3/3] Temporarily remove riscv64 inline asm support Riscv support is not currently being tested so it is likely broken. Removing it may avoid confusion in the future. --- src/inline_asm.rs | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/src/inline_asm.rs b/src/inline_asm.rs index 402dc457317..b6ee0500a40 100644 --- a/src/inline_asm.rs +++ b/src/inline_asm.rs @@ -706,12 +706,6 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { // rbx is reserved by LLVM for the "base pointer", so rustc doesn't allow using it generated_asm.push_str(" mov rbx,rdi\n"); } - InlineAsmArch::RiscV64 => { - generated_asm.push_str(" addi sp, sp, -16\n"); - generated_asm.push_str(" sd ra, 8(sp)\n"); - generated_asm.push_str(" sd s0, 0(sp)\n"); - generated_asm.push_str(" mv s0, a0\n"); - } InlineAsmArch::AArch64 => { generated_asm.push_str(" stp fp, lr, [sp, #-32]!\n"); generated_asm.push_str(" mov fp, sp\n"); @@ -730,12 +724,6 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { generated_asm.push_str(" pop rbp\n"); generated_asm.push_str(" ret\n"); } - InlineAsmArch::RiscV64 => { - generated_asm.push_str(" ld s0, 0(sp)\n"); - generated_asm.push_str(" ld ra, 8(sp)\n"); - generated_asm.push_str(" addi sp, sp, 16\n"); - generated_asm.push_str(" ret\n"); - } InlineAsmArch::AArch64 => { generated_asm.push_str(" ldr x19, [sp, #24]\n"); generated_asm.push_str(" ldp fp, lr, [sp], #32\n"); @@ -750,9 +738,6 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { InlineAsmArch::X86_64 => { generated_asm.push_str(" ud2\n"); } - InlineAsmArch::RiscV64 => { - generated_asm.push_str(" ebreak\n"); - } InlineAsmArch::AArch64 => { generated_asm.push_str(" brk #0x1"); } @@ -772,11 +757,6 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap(); generated_asm.push('\n'); } - InlineAsmArch::RiscV64 => { - generated_asm.push_str(" sd "); - reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap(); - writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap(); - } InlineAsmArch::AArch64 => { generated_asm.push_str(" str "); reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap(); @@ -798,11 +778,6 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> { reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap(); writeln!(generated_asm, ", [rbx+0x{:x}]", offset.bytes()).unwrap(); } - InlineAsmArch::RiscV64 => { - generated_asm.push_str(" ld "); - reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap(); - writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap(); - } InlineAsmArch::AArch64 => { generated_asm.push_str(" ldr "); reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap();