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support crc32 with 8-bit and 16-bit inputs, and add crc64 support

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Folkert 2024-05-11 21:44:08 +02:00
parent 7b50189dce
commit e7b6662464
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1 changed files with 13 additions and 2 deletions
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15
src/intrinsics/llvm_x86.rs
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@ -832,16 +832,27 @@ fn select4(
} }
} }
"llvm.x86.sse42.crc32.32.32" => { "llvm.x86.sse42.crc32.32.8"
| "llvm.x86.sse42.crc32.32.16"
| "llvm.x86.sse42.crc32.32.32"
| "llvm.x86.sse42.crc32.64.64" => {
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#ig_expand=1419&text=_mm_crc32_u32 // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#ig_expand=1419&text=_mm_crc32_u32
intrinsic_args!(fx, args => (crc, v); intrinsic); intrinsic_args!(fx, args => (crc, v); intrinsic);
let crc = crc.load_scalar(fx); let crc = crc.load_scalar(fx);
let v = v.load_scalar(fx); let v = v.load_scalar(fx);
let asm = match intrinsic {
"llvm.x86.sse42.crc32.32.8" => "crc32 eax, dl",
"llvm.x86.sse42.crc32.32.16" => "crc32 eax, dx",
"llvm.x86.sse42.crc32.32.32" => "crc32 eax, edx",
"llvm.x86.sse42.crc32.64.64" => "crc32 rax, rdx",
_ => unreachable!(),
};
codegen_inline_asm_inner( codegen_inline_asm_inner(
fx, fx,
&[InlineAsmTemplatePiece::String("crc32 eax, edx".to_string())], &[InlineAsmTemplatePiece::String(asm.to_string())],
&[ &[
CInlineAsmOperand::InOut { CInlineAsmOperand::InOut {
reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax)), reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax)),