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Merge pull request #187 from GuillaumeGomez/invalid-conversion

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Prevent invalid intrinsics conversion generation
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antoyo 2022-06-24 12:57:54 -04:00 committed by GitHub
commit d6aadc684b
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 65 additions and 44 deletions
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88
src/intrinsic/archs.rs
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@ -5995,8 +5995,8 @@
"llvm.x86.avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask",
"llvm.x86.avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask",
"llvm.x86.avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask",
"llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask",
"llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask",
"llvm.x86.avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask",
"llvm.x86.avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask",
"llvm.x86.avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask",
@ -6110,8 +6110,8 @@
"llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask",
"llvm.x86.avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask",
"llvm.x86.avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask",
"llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask",
"llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask",
"llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask",
"llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask",
"llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask",
@ -6157,8 +6157,8 @@
"llvm.x86.avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask",
"llvm.x86.avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask",
"llvm.x86.avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask",
"llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask",
"llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask",
"llvm.x86.avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask",
"llvm.x86.avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask",
"llvm.x86.avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask",
@ -6205,16 +6205,16 @@
"llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask",
"llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask",
"llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask",
"llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask",
"llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask",
"llvm.x86.avx512.mask.getmant.pd.128" => "__builtin_ia32_getmantpd128_mask",
"llvm.x86.avx512.mask.getmant.pd.256" => "__builtin_ia32_getmantpd256_mask",
"llvm.x86.avx512.mask.getmant.pd.512" => "__builtin_ia32_getmantpd512_mask",
"llvm.x86.avx512.mask.getmant.ps.128" => "__builtin_ia32_getmantps128_mask",
"llvm.x86.avx512.mask.getmant.ps.256" => "__builtin_ia32_getmantps256_mask",
"llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask",
"llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask",
"llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask",
"llvm.x86.avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask",
"llvm.x86.avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask",
"llvm.x86.avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask",
@ -6239,16 +6239,16 @@
"llvm.x86.avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask",
"llvm.x86.avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask",
"llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask",
"llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask",
"llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask",
"llvm.x86.avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask",
"llvm.x86.avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask",
"llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask",
"llvm.x86.avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask",
"llvm.x86.avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask",
"llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask",
"llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask",
"llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask",
"llvm.x86.avx512.mask.move.sd" => "__builtin_ia32_movsd_mask",
"llvm.x86.avx512.mask.move.ss" => "__builtin_ia32_movss_mask",
"llvm.x86.avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask",
@ -6257,8 +6257,8 @@
"llvm.x86.avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask",
"llvm.x86.avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask",
"llvm.x86.avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask",
"llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask",
"llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask",
"llvm.x86.avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask",
"llvm.x86.avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask",
"llvm.x86.avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask",
@ -6743,8 +6743,8 @@
"llvm.x86.avx512.mask.range.ps.128" => "__builtin_ia32_rangeps128_mask",
"llvm.x86.avx512.mask.range.ps.256" => "__builtin_ia32_rangeps256_mask",
"llvm.x86.avx512.mask.range.ps.512" => "__builtin_ia32_rangeps512_mask",
"llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask",
"llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask",
"llvm.x86.avx512.mask.reduce.pd.128" => "__builtin_ia32_reducepd128_mask",
"llvm.x86.avx512.mask.reduce.pd.256" => "__builtin_ia32_reducepd256_mask",
"llvm.x86.avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask",
@ -6759,16 +6759,16 @@
"llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask",
"llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask",
"llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask",
"llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask",
"llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask",
"llvm.x86.avx512.mask.scalef.pd.128" => "__builtin_ia32_scalefpd128_mask",
"llvm.x86.avx512.mask.scalef.pd.256" => "__builtin_ia32_scalefpd256_mask",
"llvm.x86.avx512.mask.scalef.pd.512" => "__builtin_ia32_scalefpd512_mask",
"llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask",
"llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask",
"llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask",
"llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask",
"llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask",
"llvm.x86.avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask",
"llvm.x86.avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask",
"llvm.x86.avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask",
@ -6789,8 +6789,8 @@
"llvm.x86.avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask",
"llvm.x86.avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask",
"llvm.x86.avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
"llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask",
"llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask",
"llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask",
"llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask",
"llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask",
@ -6802,8 +6802,8 @@
"llvm.x86.avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask",
"llvm.x86.avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask",
"llvm.x86.avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask",
"llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask",
"llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask",
"llvm.x86.avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask",
"llvm.x86.avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask",
"llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask",
@ -7121,9 +7121,9 @@
"llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask",
"llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask",
"llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask",
"llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask",
// [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask",
"llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask",
// [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask",
"llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd",
"llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless",
@ -7137,9 +7137,9 @@
"llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask",
"llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask",
"llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask",
"llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask",
// [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask",
"llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask",
// [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask",
"llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df",
"llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si",
@ -7237,21 +7237,21 @@
"llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_512",
"llvm.x86.avx512fp16.add.ph.512" => "__builtin_ia32_addph512",
"llvm.x86.avx512fp16.div.ph.512" => "__builtin_ia32_divph512",
"llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask",
"llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask",
"llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask",
"llvm.x86.avx512fp16.mask.fpclass.sh" => "__builtin_ia32_fpclasssh_mask",
"llvm.x86.avx512fp16.mask.getexp.ph.128" => "__builtin_ia32_getexpph128_mask",
"llvm.x86.avx512fp16.mask.getexp.ph.256" => "__builtin_ia32_getexpph256_mask",
"llvm.x86.avx512fp16.mask.getexp.ph.512" => "__builtin_ia32_getexpph512_mask",
"llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask",
"llvm.x86.avx512fp16.mask.getmant.ph.128" => "__builtin_ia32_getmantph128_mask",
"llvm.x86.avx512fp16.mask.getmant.ph.256" => "__builtin_ia32_getmantph256_mask",
"llvm.x86.avx512fp16.mask.getmant.ph.512" => "__builtin_ia32_getmantph512_mask",
"llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask",
"llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask",
"llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask",
"llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask",
"llvm.x86.avx512fp16.mask.rcp.ph.128" => "__builtin_ia32_rcpph128_mask",
"llvm.x86.avx512fp16.mask.rcp.ph.256" => "__builtin_ia32_rcpph256_mask",
"llvm.x86.avx512fp16.mask.rcp.ph.512" => "__builtin_ia32_rcpph512_mask",
@ -7263,7 +7263,7 @@
"llvm.x86.avx512fp16.mask.rndscale.ph.128" => "__builtin_ia32_rndscaleph_128_mask",
"llvm.x86.avx512fp16.mask.rndscale.ph.256" => "__builtin_ia32_rndscaleph_256_mask",
"llvm.x86.avx512fp16.mask.rndscale.ph.512" => "__builtin_ia32_rndscaleph_mask",
"llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask",
"llvm.x86.avx512fp16.mask.rsqrt.ph.128" => "__builtin_ia32_rsqrtph128_mask",
"llvm.x86.avx512fp16.mask.rsqrt.ph.256" => "__builtin_ia32_rsqrtph256_mask",
"llvm.x86.avx512fp16.mask.rsqrt.ph.512" => "__builtin_ia32_rsqrtph512_mask",
@ -7271,8 +7271,8 @@
"llvm.x86.avx512fp16.mask.scalef.ph.128" => "__builtin_ia32_scalefph128_mask",
"llvm.x86.avx512fp16.mask.scalef.ph.256" => "__builtin_ia32_scalefph256_mask",
"llvm.x86.avx512fp16.mask.scalef.ph.512" => "__builtin_ia32_scalefph512_mask",
"llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask",
"llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask",
"llvm.x86.avx512fp16.mask.vcvtdq2ph.128" => "__builtin_ia32_vcvtdq2ph128_mask",
"llvm.x86.avx512fp16.mask.vcvtpd2ph.128" => "__builtin_ia32_vcvtpd2ph128_mask",
"llvm.x86.avx512fp16.mask.vcvtpd2ph.256" => "__builtin_ia32_vcvtpd2ph256_mask",
@ -7306,10 +7306,10 @@
"llvm.x86.avx512fp16.mask.vcvtps2phx.512" => "__builtin_ia32_vcvtps2phx512_mask",
"llvm.x86.avx512fp16.mask.vcvtqq2ph.128" => "__builtin_ia32_vcvtqq2ph128_mask",
"llvm.x86.avx512fp16.mask.vcvtqq2ph.256" => "__builtin_ia32_vcvtqq2ph256_mask",
"llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask",
"llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask",
"llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask",
"llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask",
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask",
"llvm.x86.avx512fp16.mask.vcvttph2dq.128" => "__builtin_ia32_vcvttph2dq128_mask",
"llvm.x86.avx512fp16.mask.vcvttph2dq.256" => "__builtin_ia32_vcvttph2dq256_mask",
"llvm.x86.avx512fp16.mask.vcvttph2dq.512" => "__builtin_ia32_vcvttph2dq512_mask",

19
src/intrinsic/llvm.rs
View File

@ -618,6 +618,25 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
"llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_mask_round",
"llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_mask_round",
"llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_mask_round",
"llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_mask_round",
"llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_mask_round",
"llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask_round",
"llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask_round",
"llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask_round",
"llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask_round",
"llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_mask_round",
"llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_mask_round",
"llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_mask_round",
"llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_mask_round",
"llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_mask_round",
"llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_mask_round",
"llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_mask_round",
"llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_mask_round",
"llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_mask_round",
"llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_mask_round",
"llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_mask_round",
"llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_mask_round",
"llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_mask_round",
"llvm.x86.aesni.aesenc.256" => "__builtin_ia32_vaesenc_v32qi",
"llvm.x86.aesni.aesenclast.256" => "__builtin_ia32_vaesenclast_v32qi",
"llvm.x86.aesni.aesdec.256" => "__builtin_ia32_vaesdec_v32qi",

2
tools/generate_intrinsics.py
View File

@ -182,6 +182,8 @@ def update_intrinsics(llvm_path, llvmint, llvmint2):
for entry in intrinsics[arch]:
if entry[2] == True: # if it is a duplicate
out.write(' // [DUPLICATE]: "{}" => "{}",\n'.format(entry[0], entry[1]))
elif "_round_mask" in entry[1]:
out.write(' // [INVALID CONVERSION]: "{}" => "{}",\n'.format(entry[0], entry[1]))
else:
out.write(' "{}" => "{}",\n'.format(entry[0], entry[1]))
out.write(' _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n')