Merge pull request #1495 from folkertdev/add-llvm-sse2-cvtps2dq
add `llvm.x86.sse2.cvtps2dq`
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commit
c511676a62
@ -251,6 +251,9 @@ unsafe fn test_simd() {
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test_mm_add_epi8();
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test_mm_add_pd();
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test_mm_cvtepi8_epi16();
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#[cfg(not(jit))]
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test_mm_cvtps_epi32();
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test_mm_cvttps_epi32();
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test_mm_cvtsi128_si64();
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test_mm_extract_epi8();
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@ -476,6 +479,41 @@ unsafe fn test_mm256_permutevar8x32_epi32() {
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assert_eq_m256i(r, e);
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}
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#[cfg(target_arch = "x86_64")]
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#[target_feature(enable = "avx2")]
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#[cfg(not(jit))]
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unsafe fn test_mm_cvtps_epi32() {
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let floats: [f32; 4] = [1.5, -2.5, i32::MAX as f32 + 1.0, f32::NAN];
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let float_vec = _mm_loadu_ps(floats.as_ptr());
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let int_vec = _mm_cvtps_epi32(float_vec);
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let mut ints: [i32; 4] = [0; 4];
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_mm_storeu_si128(ints.as_mut_ptr() as *mut __m128i, int_vec);
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// this is very different from `floats.map(|f| f as i32)`!
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let expected_ints: [i32; 4] = [2, -2, i32::MIN, i32::MIN];
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assert_eq!(ints, expected_ints);
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}
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#[cfg(target_arch = "x86_64")]
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#[target_feature(enable = "avx2")]
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unsafe fn test_mm_cvttps_epi32() {
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let floats: [f32; 4] = [1.5, -2.5, i32::MAX as f32 + 1.0, f32::NAN];
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let float_vec = _mm_loadu_ps(floats.as_ptr());
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let int_vec = _mm_cvttps_epi32(float_vec);
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let mut ints: [i32; 4] = [0; 4];
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_mm_storeu_si128(ints.as_mut_ptr() as *mut __m128i, int_vec);
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// this is very different from `floats.map(|f| f as i32)`!
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let expected_ints: [i32; 4] = [1, -2, i32::MIN, i32::MIN];
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assert_eq!(ints, expected_ints);
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}
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fn test_checked_mul() {
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let u: Option<u8> = u8::from_str_radix("1000", 10).ok();
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assert_eq!(u, None);
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@ -459,11 +459,20 @@ fn select4(
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intrinsic_args!(fx, args => (a); intrinsic);
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let a = a.load_scalar(fx);
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let value = fx.bcx.ins().x86_cvtt2dq(types::I32X4, a);
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let cvalue = CValue::by_val(value, ret.layout());
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ret.write_cvalue(fx, cvalue);
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}
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"llvm.x86.sse2.cvtps2dq" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtps_epi32
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intrinsic_args!(fx, args => (a); intrinsic);
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let a = a.load_scalar(fx);
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// Using inline asm instead of fcvt_to_sint_sat as unrepresentable values are turned
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// into 0x80000000 for which Cranelift doesn't have a native instruction.
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codegen_inline_asm_inner(
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fx,
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&[InlineAsmTemplatePiece::String(format!("cvttps2dq xmm0, xmm0"))],
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&[InlineAsmTemplatePiece::String(format!("cvtps2dq xmm0, xmm0"))],
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&[CInlineAsmOperand::InOut {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::xmm0)),
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_late: true,
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