Remove the remaining simd intrinsic macros
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1ae27ea6aa
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@ -17,54 +17,6 @@ fn report_simd_type_validation_error(
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crate::trap::trap_unreachable(fx, "compilation should not have succeeded");
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crate::trap::trap_unreachable(fx, "compilation should not have succeeded");
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}
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}
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macro simd_int_binop($fx:expr, $intrinsic:ident, $span:ident, $op_u:ident|$op_s:ident($x:ident, $y:ident) -> $ret:ident) {
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if !$x.layout().ty.is_simd() {
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report_simd_type_validation_error($fx, $intrinsic, $span, $x.layout().ty);
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return;
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}
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// FIXME use vector instructions when possible
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simd_pair_for_each_lane($fx, $x, $y, $ret, &|fx, lane_ty, _ret_lane_ty, x_lane, y_lane| {
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match lane_ty.kind() {
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ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
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ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
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_ => unreachable!("{:?}", lane_ty),
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}
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});
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}
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macro simd_int_flt_binop($fx:expr, $intrinsic:ident, $span:ident, $op_u:ident|$op_s:ident|$op_f:ident($x:ident, $y:ident) -> $ret:ident) {
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if !$x.layout().ty.is_simd() {
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report_simd_type_validation_error($fx, $intrinsic, $span, $x.layout().ty);
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return;
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}
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// FIXME use vector instructions when possible
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simd_pair_for_each_lane($fx, $x, $y, $ret, &|fx, lane_ty, _ret_lane_ty, x_lane, y_lane| {
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match lane_ty.kind() {
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ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
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ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
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ty::Float(_) => fx.bcx.ins().$op_f(x_lane, y_lane),
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_ => unreachable!("{:?}", lane_ty),
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}
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});
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}
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macro simd_flt_binop($fx:expr, $intrinsic:ident, $span:ident, $op:ident($x:ident, $y:ident) -> $ret:ident) {
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if !$x.layout().ty.is_simd() {
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report_simd_type_validation_error($fx, $intrinsic, $span, $x.layout().ty);
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return;
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}
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// FIXME use vector instructions when possible
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simd_pair_for_each_lane($fx, $x, $y, $ret, &|fx, lane_ty, _ret_lane_ty, x_lane, y_lane| {
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match lane_ty.kind() {
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ty::Float(_) => fx.bcx.ins().$op(x_lane, y_lane),
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_ => unreachable!("{:?}", lane_ty),
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}
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});
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}
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pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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intrinsic: Symbol,
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intrinsic: Symbol,
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@ -142,6 +94,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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(ty::Float(_), sym::simd_ge) => {
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(ty::Float(_), sym::simd_ge) => {
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fx.bcx.ins().fcmp(FloatCC::GreaterThanOrEqual, x_lane, y_lane)
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fx.bcx.ins().fcmp(FloatCC::GreaterThanOrEqual, x_lane, y_lane)
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}
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}
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_ => unreachable!(),
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_ => unreachable!(),
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};
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};
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@ -327,17 +280,34 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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});
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});
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};
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};
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simd_add, (c x, c y) {
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simd_add | simd_sub | simd_mul | simd_div, (c x, c y) {
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simd_int_flt_binop!(fx, intrinsic, span, iadd|iadd|fadd(x, y) -> ret);
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if !x.layout().ty.is_simd() {
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};
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report_simd_type_validation_error(fx, intrinsic, span, x.layout().ty);
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simd_sub, (c x, c y) {
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return;
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simd_int_flt_binop!(fx, intrinsic, span, isub|isub|fsub(x, y) -> ret);
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}
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};
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simd_mul, (c x, c y) {
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// FIXME use vector instructions when possible
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simd_int_flt_binop!(fx, intrinsic, span, imul|imul|fmul(x, y) -> ret);
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simd_pair_for_each_lane(fx, x, y, ret, &|fx, lane_ty, _ret_lane_ty, x_lane, y_lane| match (
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};
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lane_ty.kind(),
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simd_div, (c x, c y) {
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intrinsic,
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simd_int_flt_binop!(fx, intrinsic, span, udiv|sdiv|fdiv(x, y) -> ret);
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) {
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(ty::Uint(_), sym::simd_add) => fx.bcx.ins().iadd(x_lane, y_lane),
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(ty::Uint(_), sym::simd_sub) => fx.bcx.ins().isub(x_lane, y_lane),
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(ty::Uint(_), sym::simd_mul) => fx.bcx.ins().imul(x_lane, y_lane),
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(ty::Uint(_), sym::simd_div) => fx.bcx.ins().udiv(x_lane, y_lane),
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(ty::Int(_), sym::simd_add) => fx.bcx.ins().iadd(x_lane, y_lane),
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(ty::Int(_), sym::simd_sub) => fx.bcx.ins().isub(x_lane, y_lane),
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(ty::Int(_), sym::simd_mul) => fx.bcx.ins().imul(x_lane, y_lane),
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(ty::Int(_), sym::simd_div) => fx.bcx.ins().sdiv(x_lane, y_lane),
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(ty::Float(_), sym::simd_add) => fx.bcx.ins().fadd(x_lane, y_lane),
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(ty::Float(_), sym::simd_sub) => fx.bcx.ins().fsub(x_lane, y_lane),
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(ty::Float(_), sym::simd_mul) => fx.bcx.ins().fmul(x_lane, y_lane),
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(ty::Float(_), sym::simd_div) => fx.bcx.ins().fdiv(x_lane, y_lane),
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_ => unreachable!(),
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});
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};
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};
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simd_rem, (c x, c y) {
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simd_rem, (c x, c y) {
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if !x.layout().ty.is_simd() {
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if !x.layout().ty.is_simd() {
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@ -365,20 +335,31 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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}
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}
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});
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});
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};
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};
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simd_shl, (c x, c y) {
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simd_shl | simd_shr | simd_and | simd_or | simd_xor, (c x, c y) {
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simd_int_binop!(fx, intrinsic, span, ishl|ishl(x, y) -> ret);
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if !x.layout().ty.is_simd() {
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};
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report_simd_type_validation_error(fx, intrinsic, span, x.layout().ty);
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simd_shr, (c x, c y) {
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return;
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simd_int_binop!(fx, intrinsic, span, ushr|sshr(x, y) -> ret);
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}
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};
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simd_and, (c x, c y) {
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// FIXME use vector instructions when possible
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simd_int_binop!(fx, intrinsic, span, band|band(x, y) -> ret);
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simd_pair_for_each_lane(fx, x, y, ret, &|fx, lane_ty, _ret_lane_ty, x_lane, y_lane| match (
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};
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lane_ty.kind(),
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simd_or, (c x, c y) {
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intrinsic,
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simd_int_binop!(fx, intrinsic, span, bor|bor(x, y) -> ret);
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) {
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};
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(ty::Uint(_), sym::simd_shl) => fx.bcx.ins().ishl(x_lane, y_lane),
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simd_xor, (c x, c y) {
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(ty::Uint(_), sym::simd_shr) => fx.bcx.ins().ushr(x_lane, y_lane),
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simd_int_binop!(fx, intrinsic, span, bxor|bxor(x, y) -> ret);
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(ty::Uint(_), sym::simd_and) => fx.bcx.ins().band(x_lane, y_lane),
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(ty::Uint(_), sym::simd_or) => fx.bcx.ins().bor(x_lane, y_lane),
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(ty::Uint(_), sym::simd_xor) => fx.bcx.ins().bxor(x_lane, y_lane),
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(ty::Int(_), sym::simd_shl) => fx.bcx.ins().ishl(x_lane, y_lane),
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(ty::Int(_), sym::simd_shr) => fx.bcx.ins().sshr(x_lane, y_lane),
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(ty::Int(_), sym::simd_and) => fx.bcx.ins().band(x_lane, y_lane),
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(ty::Int(_), sym::simd_or) => fx.bcx.ins().bor(x_lane, y_lane),
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(ty::Int(_), sym::simd_xor) => fx.bcx.ins().bxor(x_lane, y_lane),
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_ => unreachable!(),
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});
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};
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};
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simd_fma, (c a, c b, c c) {
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simd_fma, (c a, c b, c c) {
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@ -407,11 +388,24 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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}
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}
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};
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};
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simd_fmin, (c x, c y) {
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simd_fmin | simd_fmax, (c x, c y) {
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simd_flt_binop!(fx, intrinsic, span, fmin(x, y) -> ret);
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if !x.layout().ty.is_simd() {
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};
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report_simd_type_validation_error(fx, intrinsic, span, x.layout().ty);
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simd_fmax, (c x, c y) {
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return;
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simd_flt_binop!(fx, intrinsic, span, fmax(x, y) -> ret);
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}
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// FIXME use vector instructions when possible
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simd_pair_for_each_lane(fx, x, y, ret, &|fx, lane_ty, _ret_lane_ty, x_lane, y_lane| {
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match lane_ty.kind() {
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ty::Float(_) => {},
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_ => unreachable!("{:?}", lane_ty),
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}
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match intrinsic {
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sym::simd_fmin => fx.bcx.ins().fmin(x_lane, y_lane),
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sym::simd_fmax => fx.bcx.ins().fmax(x_lane, y_lane),
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_ => unreachable!(),
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}
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});
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};
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};
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simd_round, (c a) {
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simd_round, (c a) {
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