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Fix simd_select_bitmask on big-endian systems

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The mask input for simd_select_bitmask depends on the host byteorder
in the same way as the mask output of simd_bitmask does.  Fix the
implementation to work on both big- and little-endian systems.
This commit is contained in:
Ulrich Weigand 2024-02-19 12:33:08 +01:00
parent e4584e84d9
commit b886be124d
1 changed files with 7 additions and 1 deletions
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8
src/intrinsics/simd.rs
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@ -853,7 +853,13 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
};
for lane in 0..lane_count {
let m_lane = fx.bcx.ins().ushr_imm(m, u64::from(lane) as i64);
// The bit order of the mask depends on the byte endianness, LSB-first for
// little endian and MSB-first for big endian.
let mask_lane = match fx.tcx.sess.target.endian {
Endian::Big => lane_count - 1 - lane,
Endian::Little => lane,
};
let m_lane = fx.bcx.ins().ushr_imm(m, u64::from(mask_lane) as i64);
let m_lane = fx.bcx.ins().band_imm(m_lane, 1);
let a_lane = a.value_lane(fx, lane).load_scalar(fx);
let b_lane = b.value_lane(fx, lane).load_scalar(fx);