mikros/rust
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add more SIMD

Browse Source
This commit is contained in:
Antoni Boucher 2022-06-05 17:16:27 -04:00
parent e5a1bb2f59
commit b55bd956dc
1 changed files with 45 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
src/intrinsic/llvm.rs
View File

@ -171,7 +171,10 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc
new_args.push(last_arg);
args = new_args.into();
},
"__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => {
"__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" | "__builtin_ia32_vpmadd52huq512_mask"
| "__builtin_ia32_vpmadd52luq512_mask" | "__builtin_ia32_vpmadd52huq256_mask" | "__builtin_ia32_vpmadd52luq256_mask"
| "__builtin_ia32_vpmadd52huq128_mask"
=> {
let mut new_args = args.to_vec();
let last_arg = new_args.pop().expect("last arg");
let arg4_type = gcc_func.get_param_type(3);
@ -504,6 +507,42 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
"llvm.x86.xsavec" => "__builtin_ia32_xsavec",
"llvm.x86.addcarry.32" => "__builtin_ia32_addcarryx_u32",
"llvm.x86.subborrow.32" => "__builtin_ia32_sbb_u32",
"llvm.x86.avx512.mask.compress.store.w.512" => "__builtin_ia32_compressstoreuhi512_mask",
"llvm.x86.avx512.mask.compress.store.w.256" => "__builtin_ia32_compressstoreuhi256_mask",
"llvm.x86.avx512.mask.compress.store.w.128" => "__builtin_ia32_compressstoreuhi128_mask",
"llvm.x86.avx512.mask.compress.store.b.512" => "__builtin_ia32_compressstoreuqi512_mask",
"llvm.x86.avx512.mask.compress.store.b.256" => "__builtin_ia32_compressstoreuqi256_mask",
"llvm.x86.avx512.mask.compress.store.b.128" => "__builtin_ia32_compressstoreuqi128_mask",
"llvm.x86.avx512.mask.compress.w.512" => "__builtin_ia32_compressstoreuhi512_mask",
"llvm.x86.avx512.mask.compress.w.256" => "__builtin_ia32_compresshi256_mask",
"llvm.x86.avx512.mask.compress.w.128" => "__builtin_ia32_compresshi128_mask",
"llvm.x86.avx512.mask.compress.b.512" => "__builtin_ia32_compressstoreuqi512_mask",
"llvm.x86.avx512.mask.compress.b.256" => "__builtin_ia32_compressqi256_mask",
"llvm.x86.avx512.mask.compress.b.128" => "__builtin_ia32_compressqi128_mask",
"llvm.x86.avx512.mask.expand.w.512" => "__builtin_ia32_expandhi512_mask",
"llvm.x86.avx512.mask.expand.w.256" => "__builtin_ia32_expandhi256_mask",
"llvm.x86.avx512.mask.expand.w.128" => "__builtin_ia32_expandhi128_mask",
"llvm.x86.avx512.mask.expand.b.512" => "__builtin_ia32_expandqi512_mask",
"llvm.x86.avx512.mask.expand.b.256" => "__builtin_ia32_expandqi256_mask",
"llvm.x86.avx512.mask.expand.b.128" => "__builtin_ia32_expandqi128_mask",
"llvm.fshl.v8i64" => "__builtin_ia32_vpshldv_v8di",
"llvm.fshl.v4i64" => "__builtin_ia32_vpshldv_v4di",
"llvm.fshl.v2i64" => "__builtin_ia32_vpshldv_v2di",
"llvm.fshl.v16i32" => "__builtin_ia32_vpshldv_v16si",
"llvm.fshl.v8i32" => "__builtin_ia32_vpshldv_v8si",
"llvm.fshl.v4i32" => "__builtin_ia32_vpshldv_v4si",
"llvm.fshl.v32i16" => "__builtin_ia32_vpshldv_v32hi",
"llvm.fshl.v16i16" => "__builtin_ia32_vpshldv_v16hi",
"llvm.fshl.v8i16" => "__builtin_ia32_vpshldv_v8hi",
"llvm.fshr.v8i64" => "__builtin_ia32_vpshrdv_v8di",
"llvm.fshr.v4i64" => "__builtin_ia32_vpshrdv_v4di",
"llvm.fshr.v2i64" => "__builtin_ia32_vpshrdv_v2di",
"llvm.fshr.v16i32" => "__builtin_ia32_vpshrdv_v16si",
"llvm.fshr.v8i32" => "__builtin_ia32_vpshrdv_v8si",
"llvm.fshr.v4i32" => "__builtin_ia32_vpshrdv_v4si",
"llvm.fshr.v32i16" => "__builtin_ia32_vpshrdv_v32hi",
"llvm.fshr.v16i16" => "__builtin_ia32_vpshrdv_v16hi",
"llvm.fshr.v8i16" => "__builtin_ia32_vpshrdv_v8hi",
// The above doc points to unknown builtins for the following, so override them:
"llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si",
@ -630,6 +669,11 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
"llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask",
"llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask",
"llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask",
"llvm.x86.avx512.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask",
"llvm.x86.avx512.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask",
"llvm.x86.avx512.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask",
"llvm.x86.avx512.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask",
"llvm.x86.avx512.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask",
// NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py
_ => include!("archs.rs"),