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Remove stub support for 32bit inline assembly

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Cranelift doesn't support any 32bit target yet and this helps with
keeping everything in sync.
This commit is contained in:
bjorn3 2023-10-05 18:55:18 +00:00
parent f1ede97b14
commit a47b9fd2e6
1 changed files with 2 additions and 42 deletions
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44
src/inline_asm.rs
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@ -699,20 +699,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
fn prologue(generated_asm: &mut String, arch: InlineAsmArch) { fn prologue(generated_asm: &mut String, arch: InlineAsmArch) {
match arch { match arch {
InlineAsmArch::X86 => {
generated_asm.push_str(" push ebp\n");
generated_asm.push_str(" mov ebp,[esp+8]\n");
}
InlineAsmArch::X86_64 => { InlineAsmArch::X86_64 => {
generated_asm.push_str(" push rbp\n"); generated_asm.push_str(" push rbp\n");
generated_asm.push_str(" mov rbp,rdi\n"); generated_asm.push_str(" mov rbp,rdi\n");
} }
InlineAsmArch::RiscV32 => {
generated_asm.push_str(" addi sp, sp, -8\n");
generated_asm.push_str(" sw ra, 4(sp)\n");
generated_asm.push_str(" sw s0, 0(sp)\n");
generated_asm.push_str(" mv s0, a0\n");
}
InlineAsmArch::RiscV64 => { InlineAsmArch::RiscV64 => {
generated_asm.push_str(" addi sp, sp, -16\n"); generated_asm.push_str(" addi sp, sp, -16\n");
generated_asm.push_str(" sd ra, 8(sp)\n"); generated_asm.push_str(" sd ra, 8(sp)\n");
@ -725,20 +715,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
fn epilogue(generated_asm: &mut String, arch: InlineAsmArch) { fn epilogue(generated_asm: &mut String, arch: InlineAsmArch) {
match arch { match arch {
InlineAsmArch::X86 => {
generated_asm.push_str(" pop ebp\n");
generated_asm.push_str(" ret\n");
}
InlineAsmArch::X86_64 => { InlineAsmArch::X86_64 => {
generated_asm.push_str(" pop rbp\n"); generated_asm.push_str(" pop rbp\n");
generated_asm.push_str(" ret\n"); generated_asm.push_str(" ret\n");
} }
InlineAsmArch::RiscV32 => {
generated_asm.push_str(" lw s0, 0(sp)\n");
generated_asm.push_str(" lw ra, 4(sp)\n");
generated_asm.push_str(" addi sp, sp, 8\n");
generated_asm.push_str(" ret\n");
}
InlineAsmArch::RiscV64 => { InlineAsmArch::RiscV64 => {
generated_asm.push_str(" ld s0, 0(sp)\n"); generated_asm.push_str(" ld s0, 0(sp)\n");
generated_asm.push_str(" ld ra, 8(sp)\n"); generated_asm.push_str(" ld ra, 8(sp)\n");
@ -751,10 +731,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
fn epilogue_noreturn(generated_asm: &mut String, arch: InlineAsmArch) { fn epilogue_noreturn(generated_asm: &mut String, arch: InlineAsmArch) {
match arch { match arch {
InlineAsmArch::X86 | InlineAsmArch::X86_64 => { InlineAsmArch::X86_64 => {
generated_asm.push_str(" ud2\n"); generated_asm.push_str(" ud2\n");
} }
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => { InlineAsmArch::RiscV64 => {
generated_asm.push_str(" ebreak\n"); generated_asm.push_str(" ebreak\n");
} }
_ => unimplemented!("epilogue_noreturn for {:?}", arch), _ => unimplemented!("epilogue_noreturn for {:?}", arch),
@ -768,21 +748,11 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
offset: Size, offset: Size,
) { ) {
match arch { match arch {
InlineAsmArch::X86 => {
write!(generated_asm, " mov [ebp+0x{:x}], ", offset.bytes()).unwrap();
reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap();
generated_asm.push('\n');
}
InlineAsmArch::X86_64 => { InlineAsmArch::X86_64 => {
write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap(); write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap();
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap(); reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
generated_asm.push('\n'); generated_asm.push('\n');
} }
InlineAsmArch::RiscV32 => {
generated_asm.push_str(" sw ");
reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap();
writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
}
InlineAsmArch::RiscV64 => { InlineAsmArch::RiscV64 => {
generated_asm.push_str(" sd "); generated_asm.push_str(" sd ");
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap(); reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
@ -799,21 +769,11 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
offset: Size, offset: Size,
) { ) {
match arch { match arch {
InlineAsmArch::X86 => {
generated_asm.push_str(" mov ");
reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap();
writeln!(generated_asm, ", [ebp+0x{:x}]", offset.bytes()).unwrap();
}
InlineAsmArch::X86_64 => { InlineAsmArch::X86_64 => {
generated_asm.push_str(" mov "); generated_asm.push_str(" mov ");
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap(); reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap(); writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap();
} }
InlineAsmArch::RiscV32 => {
generated_asm.push_str(" lw ");
reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap();
writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
}
InlineAsmArch::RiscV64 => { InlineAsmArch::RiscV64 => {
generated_asm.push_str(" ld "); generated_asm.push_str(" ld ");
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap(); reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();