Fixes to make stdarch tests compile
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parent
1777cdd644
commit
910ec42566
22
src/base.rs
22
src/base.rs
@ -83,7 +83,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_
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context.add_command_line_option("-mavx2");
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// FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU.
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// Only add if the CPU supports it.
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/*context.add_command_line_option("-mavx512f");
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context.add_command_line_option("-mavx512f");
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context.add_command_line_option("-msha");
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context.add_command_line_option("-mpclmul");
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context.add_command_line_option("-mfma");
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@ -91,7 +91,25 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_
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context.add_command_line_option("-mavx512vpopcntdq");
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context.add_command_line_option("-mavx512vl");
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context.add_command_line_option("-m64");
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context.add_command_line_option("-mbmi");*/
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context.add_command_line_option("-mbmi");
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context.add_command_line_option("-mgfni");
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context.add_command_line_option("-mavxvnni");
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context.add_command_line_option("-mavx512vnni");
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context.add_command_line_option("-mavx512bw");
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context.add_command_line_option("-mf16c");
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context.add_command_line_option("-mavx512bitalg");
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context.add_command_line_option("-maes");
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context.add_command_line_option("-mxsavec");
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context.add_command_line_option("-mbmi2");
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context.add_command_line_option("-mavx512bf16");
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context.add_command_line_option("-mrtm");
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context.add_command_line_option("-mvaes");
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context.add_command_line_option("-mvpclmulqdq");
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context.add_command_line_option("-mavx");
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context.add_command_line_option("-mavx512vbmi2");
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context.add_command_line_option("-mavx512vbmi");
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context.add_command_line_option("-mavx512ifma");
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context.add_command_line_option("-mavx512cd");
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for arg in &tcx.sess.opts.cg.llvm_args {
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context.add_command_line_option(arg);
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}
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@ -213,7 +213,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
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let actual_ty = actual_val.get_type();
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if expected_ty != actual_ty {
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if !actual_ty.is_vector() && !expected_ty.is_vector() && actual_ty.is_integral() && expected_ty.is_integral() {
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if !actual_ty.is_vector() && !expected_ty.is_vector() && (actual_ty.is_integral() && expected_ty.is_integral()) || (actual_ty.get_pointee().is_some() && expected_ty.get_pointee().is_some()) {
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self.context.new_cast(None, actual_val, expected_ty)
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}
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else if on_stack_param_indices.contains(&index) {
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@ -177,8 +177,18 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> {
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}
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let value = self.const_uint_big(self.type_ix(bitsize), data);
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// TODO(bjorn3): assert size is correct
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self.const_bitcast(value, ty)
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let bytesize = layout.size(self).bytes();
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if bitsize > 1 && ty.is_integral() && bytesize as u32 == ty.get_size() {
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// NOTE: since the intrinsic _xabort is called with a bitcast, which
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// is non-const, but expects a constant, do a normal cast instead of a bitcast.
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// FIXME(antoyo): fix bitcast to work in constant contexts.
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// TODO: perhaps only use bitcast for pointers?
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self.context.new_cast(None, value, ty)
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}
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else {
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// TODO(bjorn3): assert size is correct
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self.const_bitcast(value, ty)
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}
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}
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Scalar::Ptr(ptr, _size) => {
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let (alloc_id, offset) = ptr.into_parts();
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