Implement all vendor intrinsics used by the simd-json crate
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bjorn3
parent
ecf79a304a
commit
864973135a
@ -590,6 +590,44 @@ fn select4(
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}
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}
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"llvm.x86.sse41.packusdw" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi32&ig_expand=4912
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intrinsic_args!(fx, args => (a, b); intrinsic);
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assert_eq!(a.layout(), b.layout());
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let layout = a.layout();
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let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
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let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
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assert_eq!(lane_ty, fx.tcx.types.i32);
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assert_eq!(ret_lane_ty, fx.tcx.types.u16);
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assert_eq!(lane_count * 2, ret_lane_count);
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let min_u16 = fx.bcx.ins().iconst(types::I32, i64::from(u16::MIN));
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let max_u16 = fx.bcx.ins().iconst(types::I32, i64::from(u16::MAX));
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let ret_lane_layout = fx.layout_of(fx.tcx.types.u16);
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for idx in 0..lane_count {
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let lane = a.value_lane(fx, idx).load_scalar(fx);
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let sat = fx.bcx.ins().umax(lane, min_u16);
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let sat = fx.bcx.ins().umin(sat, max_u16);
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let res = fx.bcx.ins().ireduce(types::I16, sat);
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let res_lane = CValue::by_val(res, ret_lane_layout);
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ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
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}
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for idx in 0..lane_count {
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let lane = b.value_lane(fx, idx).load_scalar(fx);
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let sat = fx.bcx.ins().umax(lane, min_u16);
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let sat = fx.bcx.ins().umin(sat, max_u16);
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let res = fx.bcx.ins().ireduce(types::I16, sat);
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let res_lane = CValue::by_val(res, ret_lane_layout);
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ret.place_lane(fx, lane_count + idx).write_cvalue(fx, res_lane);
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}
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}
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"llvm.x86.avx2.packssdw" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi32&ig_expand=4892
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intrinsic_args!(fx, args => (a, b); intrinsic);
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@ -648,6 +686,106 @@ fn select4(
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}
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}
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"llvm.x86.pclmulqdq" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_clmulepi64_si128&ig_expand=772
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intrinsic_args!(fx, args => (a, b, imm8); intrinsic);
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assert_eq!(a.layout(), b.layout());
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let layout = a.layout();
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let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
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let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
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assert_eq!(lane_ty, fx.tcx.types.i64);
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assert_eq!(ret_lane_ty, fx.tcx.types.i64);
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assert_eq!(lane_count, 2);
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assert_eq!(ret_lane_count, 2);
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let imm8 = imm8.load_scalar(fx);
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let control0 = fx.bcx.ins().band_imm(imm8, 0b0000_0001);
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let a_lane0 = a.value_lane(fx, 0).load_scalar(fx);
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let a_lane1 = a.value_lane(fx, 1).load_scalar(fx);
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let temp1 = fx.bcx.ins().select(control0, a_lane1, a_lane0);
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let control4 = fx.bcx.ins().band_imm(imm8, 0b0001_0000);
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let b_lane0 = b.value_lane(fx, 0).load_scalar(fx);
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let b_lane1 = b.value_lane(fx, 1).load_scalar(fx);
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let temp2 = fx.bcx.ins().select(control4, b_lane1, b_lane0);
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fn extract_bit(fx: &mut FunctionCx<'_, '_, '_>, val: Value, bit: i64) -> Value {
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let tmp = fx.bcx.ins().ushr_imm(val, bit);
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fx.bcx.ins().band_imm(tmp, 1)
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}
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let mut res1 = fx.bcx.ins().iconst(types::I64, 0);
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for i in 0..=63 {
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let x = extract_bit(fx, temp1, 0);
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let y = extract_bit(fx, temp2, i);
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let mut temp = fx.bcx.ins().band(x, y);
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for j in 1..=i {
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let x = extract_bit(fx, temp1, j);
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let y = extract_bit(fx, temp2, i - j);
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let z = fx.bcx.ins().band(x, y);
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temp = fx.bcx.ins().bxor(temp, z);
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}
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let temp = fx.bcx.ins().ishl_imm(temp, i);
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res1 = fx.bcx.ins().bor(res1, temp);
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}
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ret.place_lane(fx, 0).to_ptr().store(fx, res1, MemFlags::trusted());
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let mut res2 = fx.bcx.ins().iconst(types::I64, 0);
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for i in 64..=127 {
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let mut temp = fx.bcx.ins().iconst(types::I64, 0);
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for j in i - 63..=63 {
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let x = extract_bit(fx, temp1, j);
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let y = extract_bit(fx, temp2, i - j);
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let z = fx.bcx.ins().band(x, y);
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temp = fx.bcx.ins().bxor(temp, z);
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}
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let temp = fx.bcx.ins().ishl_imm(temp, i);
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res2 = fx.bcx.ins().bor(res2, temp);
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}
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ret.place_lane(fx, 1).to_ptr().store(fx, res2, MemFlags::trusted());
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}
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"llvm.x86.avx.ptestz.256" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testz_si256&ig_expand=6945
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intrinsic_args!(fx, args => (a, b); intrinsic);
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assert_eq!(a.layout(), b.layout());
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let layout = a.layout();
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let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
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assert_eq!(lane_ty, fx.tcx.types.i64);
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assert_eq!(ret.layout().ty, fx.tcx.types.i32);
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assert_eq!(lane_count, 4);
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let a_lane0 = a.value_lane(fx, 0).load_scalar(fx);
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let a_lane1 = a.value_lane(fx, 1).load_scalar(fx);
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let a_lane2 = a.value_lane(fx, 2).load_scalar(fx);
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let a_lane3 = a.value_lane(fx, 3).load_scalar(fx);
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let b_lane0 = b.value_lane(fx, 0).load_scalar(fx);
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let b_lane1 = b.value_lane(fx, 1).load_scalar(fx);
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let b_lane2 = b.value_lane(fx, 2).load_scalar(fx);
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let b_lane3 = b.value_lane(fx, 3).load_scalar(fx);
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let zero0 = fx.bcx.ins().band(a_lane0, b_lane0);
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let zero1 = fx.bcx.ins().band(a_lane1, b_lane1);
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let zero2 = fx.bcx.ins().band(a_lane2, b_lane2);
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let zero3 = fx.bcx.ins().band(a_lane3, b_lane3);
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let all_zero0 = fx.bcx.ins().bor(zero0, zero1);
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let all_zero1 = fx.bcx.ins().bor(zero2, zero3);
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let all_zero = fx.bcx.ins().bor(all_zero0, all_zero1);
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let res = fx.bcx.ins().icmp_imm(IntCC::Equal, all_zero, 0);
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let res = CValue::by_val(
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fx.bcx.ins().uextend(types::I32, res),
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fx.layout_of(fx.tcx.types.i32),
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);
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ret.write_cvalue(fx, res);
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}
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_ => {
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fx.tcx
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.sess
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