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Reenable all cases of simd-wide-sum

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This commit is contained in:
Jubilee Young 2023-07-11 19:17:56 -07:00
parent 81dc91efbd
commit 7dc049c378
1 changed files with 3 additions and 4 deletions
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7
tests/codegen/simd-wide-sum.rs
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@ -52,9 +52,8 @@ pub fn wider_reduce_iter(x: Simd<u8, N>) -> u16 {
#[no_mangle]
// CHECK-LABEL: @wider_reduce_into_iter
pub fn wider_reduce_into_iter(x: Simd<u8, N>) -> u16 {
// FIXME MIR inlining messes up LLVM optimizations.
// WOULD-CHECK: zext <8 x i8>
// WOULD-CHECK-SAME: to <8 x i16>
// WOULD-CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
// CHECK: zext <8 x i8>
// CHECK-SAME: to <8 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
x.to_array().into_iter().map(u16::from).sum()
}