Refactor powerpc64 call ABI handling
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beetrees
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a886938671
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@ -41,59 +41,12 @@ fn is_homogeneous_aggregate<'a, Ty, C>(
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})
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}
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fn classify_ret<'a, Ty, C>(cx: &C, ret: &mut ArgAbi<'a, Ty>, abi: ABI)
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fn classify<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, abi: ABI, is_ret: bool)
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where
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Ty: TyAbiInterface<'a, C> + Copy,
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C: HasDataLayout,
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{
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if !ret.layout.is_sized() {
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// Not touching this...
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return;
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}
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if !ret.layout.is_aggregate() {
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ret.extend_integer_width_to(64);
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return;
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}
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// The ELFv1 ABI doesn't return aggregates in registers
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if abi == ELFv1 {
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ret.make_indirect();
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return;
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}
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if let Some(uniform) = is_homogeneous_aggregate(cx, ret, abi) {
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ret.cast_to(uniform);
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return;
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}
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let size = ret.layout.size;
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let bits = size.bits();
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if bits <= 128 {
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let unit = if cx.data_layout().endian == Endian::Big {
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Reg { kind: RegKind::Integer, size }
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} else if bits <= 8 {
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Reg::i8()
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} else if bits <= 16 {
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Reg::i16()
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} else if bits <= 32 {
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Reg::i32()
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} else {
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Reg::i64()
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};
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ret.cast_to(Uniform::new(unit, size));
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return;
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}
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ret.make_indirect();
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}
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fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, abi: ABI)
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where
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Ty: TyAbiInterface<'a, C> + Copy,
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C: HasDataLayout,
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{
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if !arg.layout.is_sized() {
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if arg.is_ignore() || !arg.layout.is_sized() {
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// Not touching this...
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return;
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}
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@ -102,13 +55,22 @@ fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, abi: ABI)
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return;
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}
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// The ELFv1 ABI doesn't return aggregates in registers
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if is_ret && abi == ELFv1 {
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arg.make_indirect();
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return;
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}
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if let Some(uniform) = is_homogeneous_aggregate(cx, arg, abi) {
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arg.cast_to(uniform);
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return;
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}
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let size = arg.layout.size;
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if size.bits() <= 64 {
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if is_ret && size.bits() > 128 {
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// Non-homogeneous aggregates larger than two doublewords are returned indirectly.
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arg.make_indirect();
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} else if size.bits() <= 64 {
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// Aggregates smaller than a doubleword should appear in
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// the least-significant bits of the parameter doubleword.
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arg.cast_to(Reg { kind: RegKind::Integer, size })
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@ -138,14 +100,9 @@ pub fn compute_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>)
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}
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};
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if !fn_abi.ret.is_ignore() {
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classify_ret(cx, &mut fn_abi.ret, abi);
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}
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classify(cx, &mut fn_abi.ret, abi, true);
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for arg in fn_abi.args.iter_mut() {
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if arg.is_ignore() {
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continue;
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}
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classify_arg(cx, arg, abi);
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classify(cx, arg, abi, false);
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}
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}
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132
tests/assembly/powerpc64-struct-abi.rs
Normal file
132
tests/assembly/powerpc64-struct-abi.rs
Normal file
@ -0,0 +1,132 @@
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//@ revisions: elfv1-be elfv2-be elfv2-le
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//@ assembly-output: emit-asm
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//@ compile-flags: -O
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//@[elfv1-be] compile-flags: --target powerpc64-unknown-linux-gnu
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//@[elfv1-be] needs-llvm-components: powerpc
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//@[elfv2-be] compile-flags: --target powerpc64-unknown-linux-musl
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//@[elfv2-be] needs-llvm-components: powerpc
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//@[elfv2-le] compile-flags: --target powerpc64le-unknown-linux-gnu
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//@[elfv2-le] needs-llvm-components: powerpc
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//@[elfv1-be] filecheck-flags: --check-prefix be
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//@[elfv2-be] filecheck-flags: --check-prefix be
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#![feature(no_core, lang_items)]
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#![no_std]
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#![no_core]
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#![crate_type = "lib"]
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#[lang = "sized"]
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trait Sized {}
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#[lang = "copy"]
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trait Copy {}
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#[lang = "freeze"]
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trait Freeze {}
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#[lang = "unpin"]
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trait Unpin {}
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impl Copy for u8 {}
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impl Copy for u16 {}
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impl Copy for u32 {}
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impl Copy for FiveU32s {}
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impl Copy for FiveU16s {}
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impl Copy for ThreeU8s {}
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#[repr(C)]
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struct FiveU32s(u32, u32, u32, u32, u32);
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#[repr(C)]
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struct FiveU16s(u16, u16, u16, u16, u16);
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#[repr(C)]
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struct ThreeU8s(u8, u8, u8);
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// CHECK-LABEL: read_large
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// be: lwz [[REG1:.*]], 16(4)
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// be-NEXT: stw [[REG1]], 16(3)
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// be-NEXT: ld [[REG2:.*]], 8(4)
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// be-NEXT: ld [[REG3:.*]], 0(4)
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// be-NEXT: std [[REG2]], 8(3)
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// be-NEXT: std [[REG3]], 0(3)
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// elfv2-le: lxvd2x [[REG1:.*]], 0, 4
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// elfv2-le-NEXT: lwz [[REG2:.*]], 16(4)
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// elfv2-le-NEXT: stw [[REG2]], 16(3)
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// elfv2-le-NEXT: stxvd2x [[REG1]], 0, 3
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// CHECK-NEXT: blr
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#[no_mangle]
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extern "C" fn read_large(x: &FiveU32s) -> FiveU32s {
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*x
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}
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// CHECK-LABEL: read_medium
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// elfv1-be: lhz [[REG1:.*]], 8(4)
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// elfv1-be-NEXT: ld [[REG2:.*]], 0(4)
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// elfv1-be-NEXT: sth [[REG1]], 8(3)
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// elfv1-be-NEXT: std [[REG2]], 0(3)
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// elfv2-be: lhz [[REG1:.*]], 8(3)
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// elfv2-be-NEXT: ld 3, 0(3)
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// elfv2-be-NEXT: sldi 4, [[REG1]], 48
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// elfv2-le: ld [[REG1:.*]], 0(3)
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// elfv2-le-NEXT: lhz 4, 8(3)
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// elfv2-le-NEXT: mr 3, [[REG1]]
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// CHECK-NEXT: blr
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#[no_mangle]
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extern "C" fn read_medium(x: &FiveU16s) -> FiveU16s {
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*x
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}
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// CHECK-LABEL: read_small
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// elfv1-be: lbz [[REG1:.*]], 2(4)
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// elfv1-be-NEXT: lhz [[REG2:.*]], 0(4)
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// elfv1-be-NEXT: stb [[REG1]], 2(3)
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// elfv1-be-NEXT: sth [[REG2]], 0(3)
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// elfv2-be: lhz [[REG1:.*]], 0(3)
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// elfv2-be-NEXT: lbz 3, 2(3)
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// elfv2-be-NEXT: rldimi 3, [[REG1]], 8, 0
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// elfv2-le: lbz [[REG1:.*]], 2(3)
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// elfv2-le-NEXT: lhz 3, 0(3)
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// elfv2-le-NEXT: rldimi 3, [[REG1]], 16, 0
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// CHECK-NEXT: blr
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#[no_mangle]
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extern "C" fn read_small(x: &ThreeU8s) -> ThreeU8s {
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*x
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}
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// CHECK-LABEL: write_large
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// CHECK: std 3, 0(6)
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// be-NEXT: rldicl [[REG1:.*]], 5, 32, 32
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// CHECK-NEXT: std 4, 8(6)
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// be-NEXT: stw [[REG1]], 16(6)
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// elfv2-le-NEXT: stw 5, 16(6)
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// CHECK-NEXT: blr
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#[no_mangle]
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extern "C" fn write_large(x: FiveU32s, dest: &mut FiveU32s) {
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*dest = x;
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}
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// CHECK-LABEL: write_medium
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// CHECK: std 3, 0(5)
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// be-NEXT: rldicl [[REG1:.*]], 4, 16, 48
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// be-NEXT: sth [[REG1]], 8(5)
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// elfv2-le-NEXT: sth 4, 8(5)
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// CHECK-NEXT: blr
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#[no_mangle]
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extern "C" fn write_medium(x: FiveU16s, dest: &mut FiveU16s) {
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*dest = x;
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}
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// CHECK-LABEL: write_small
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// be: stb 3, 2(4)
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// be-NEXT: srwi [[REG1:.*]], 3, 8
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// be-NEXT: sth [[REG1]], 0(4)
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// The order these instructions are emitted in changed in LLVM 18.
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// elfv2-le-DAG: sth 3, 0(4)
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// elfv2-le-DAG: srwi [[REG1:.*]], 3, 16
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// elfv2-le-NEXT: stb [[REG1]], 2(4)
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// CHECK-NEXT: blr
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#[no_mangle]
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extern "C" fn write_small(x: ThreeU8s, dest: &mut ThreeU8s) {
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*dest = x;
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}
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