Add unsigned saturating add/sub intrinsics for aarch64
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@ -180,6 +180,24 @@ unsafe fn test_vpadd_u8() {
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assert_eq!(r, e);
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assert_eq!(r, e);
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}
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}
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#[cfg(target_arch = "aarch64")]
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unsafe fn test_vqsub_u8() {
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let a = u8x8::from([1, 2, 3, 4, 5, 6, 7, 0xff]);
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let b = u8x8::from([30, 1, 1, 1, 34, 0xff, 36, 37]);
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let r: u8x8 = transmute(vqsub_u8(transmute(a), transmute(b)));
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let e = u8x8::from([0, 1, 2, 3, 0, 0, 0, 218]);
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assert_eq!(r, e);
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}
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#[cfg(target_arch = "aarch64")]
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unsafe fn test_vqadd_u8() {
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let a = u8x8::from([1, 2, 3, 4, 5, 6, 7, 0xff]);
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let b = u8x8::from([30, 1, 1, 1, 34, 0xff, 36, 37]);
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let r: u8x8 = transmute(vqadd_u8(transmute(a), transmute(b)));
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let e = u8x8::from([31, 3, 4, 5, 39, 0xff, 43, 0xff]);
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assert_eq!(r, e);
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}
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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fn main() {
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fn main() {
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unsafe {
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unsafe {
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@ -204,6 +222,9 @@ fn main() {
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test_vpadd_u16();
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test_vpadd_u16();
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test_vpadd_u32();
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test_vpadd_u32();
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test_vpadd_u8();
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test_vpadd_u8();
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test_vqsub_u8();
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test_vqadd_u8();
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}
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}
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}
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}
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@ -44,7 +44,9 @@ pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
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});
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});
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}
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}
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_ if intrinsic.starts_with("llvm.aarch64.neon.sqadd.v") => {
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_ if intrinsic.starts_with("llvm.aarch64.neon.sqadd.v")
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|| intrinsic.starts_with("llvm.aarch64.neon.uqadd.v") =>
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{
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intrinsic_args!(fx, args => (x, y); intrinsic);
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intrinsic_args!(fx, args => (x, y); intrinsic);
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simd_pair_for_each_lane_typed(fx, x, y, ret, &|fx, x_lane, y_lane| {
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simd_pair_for_each_lane_typed(fx, x, y, ret, &|fx, x_lane, y_lane| {
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@ -52,7 +54,9 @@ pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
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});
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});
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}
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}
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_ if intrinsic.starts_with("llvm.aarch64.neon.sqsub.v") => {
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_ if intrinsic.starts_with("llvm.aarch64.neon.sqsub.v")
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|| intrinsic.starts_with("llvm.aarch64.neon.uqsub.v") =>
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{
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intrinsic_args!(fx, args => (x, y); intrinsic);
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intrinsic_args!(fx, args => (x, y); intrinsic);
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simd_pair_for_each_lane_typed(fx, x, y, ret, &|fx, x_lane, y_lane| {
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simd_pair_for_each_lane_typed(fx, x, y, ret, &|fx, x_lane, y_lane| {
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