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Vxworks riscv target specs: remove redundant zicsr feature

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B I Mohammed Abbas 2024-09-25 09:46:15 +05:30
parent 4957eda2c1
commit 6d229f89ba
2 changed files with 4 additions and 4 deletions
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4
compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs
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@ -1,4 +1,4 @@
use crate::spec::{base, StackProbeType, Target, TargetOptions}; use crate::spec::{StackProbeType, Target, TargetOptions, base};
pub(crate) fn target() -> Target { pub(crate) fn target() -> Target {
Target { Target {
@ -16,7 +16,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(), cpu: "generic-rv32".into(),
llvm_abiname: "ilp32d".into(), llvm_abiname: "ilp32d".into(),
max_atomic_width: Some(32), max_atomic_width: Some(32),
features: "+m,+a,+f,+d,+c,+zicsr".into(), features: "+m,+a,+f,+d,+c".into(),
stack_probes: StackProbeType::Inline, stack_probes: StackProbeType::Inline,
..base::vxworks::opts() ..base::vxworks::opts()
}, },

4
compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs
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@ -1,4 +1,4 @@
use crate::spec::{base, StackProbeType, Target, TargetOptions}; use crate::spec::{StackProbeType, Target, TargetOptions, base};
pub(crate) fn target() -> Target { pub(crate) fn target() -> Target {
Target { Target {
@ -16,7 +16,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv64".into(), cpu: "generic-rv64".into(),
llvm_abiname: "lp64d".into(), llvm_abiname: "lp64d".into(),
max_atomic_width: Some(64), max_atomic_width: Some(64),
features: "+m,+a,+f,+d,+c,+zicsr".into(), features: "+m,+a,+f,+d,+c".into(),
stack_probes: StackProbeType::Inline, stack_probes: StackProbeType::Inline,
..base::vxworks::opts() ..base::vxworks::opts()
}, },