mikros/rust
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

asm: Match clang behavior for inlateout fixed register operands

Browse Source 
We have 2 options for representing LLVM constraints for `inlateout`
operands on a fixed register (e.g. `r0`): `={r0},0` or `={r0},{r0}`.

This PR changes the behavior to the latter, which matches the behavior
of Clang since https://reviews.llvm.org/D87279.
This commit is contained in:
Amanieu d'Antras 2022-10-15 22:46:59 +01:00
parent 6b3ede3f7b
commit 6bfe7f01dc
1 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
compiler/rustc_codegen_llvm/src/asm.rs
View File

@ -130,7 +130,7 @@ fn codegen_inline_asm(
op_idx.insert(idx, constraints.len());
constraints.push(reg_to_llvm(reg, Some(&value.layout)));
}
InlineAsmOperandRef::InOut { reg, late: _, in_value, out_place: _ } => {
InlineAsmOperandRef::InOut { reg, late, in_value, out_place: _ } => {
let value = llvm_fixup_input(
self,
in_value.immediate(),
@ -138,7 +138,16 @@ fn codegen_inline_asm(
&in_value.layout,
);
inputs.push(value);
constraints.push(format!("{}", op_idx[&idx]));
// In the case of fixed registers, we have the choice of
// either using a tied operand or duplicating the constraint.
// We prefer the latter because it matches the behavior of
// Clang.
if late && matches!(reg, InlineAsmRegOrRegClass::Reg(_)) {
constraints.push(format!("{}", reg_to_llvm(reg, Some(&in_value.layout))));
} else {
constraints.push(format!("{}", op_idx[&idx]));
}
}
InlineAsmOperandRef::SymFn { instance } => {
inputs.push(self.cx.get_fn(instance));