rustc_trans: rewrite mips64 abi
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James Cowgill
parent
f45a474bd6
commit
68042ba0d3
@ -8,50 +8,154 @@
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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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use abi::{ArgType, FnType, LayoutExt, Reg, Uniform};
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use abi::{ArgAttribute, ArgType, CastTarget, FnType, LayoutExt, PassMode, Reg, RegKind, Uniform};
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use context::CodegenCx;
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use rustc::ty::layout::{self, Size};
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use rustc::ty::layout::Size;
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fn extend_integer_width_mips(arg: &mut ArgType, bits: u64) {
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// Always sign extend u32 values on 64-bit mips
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if let layout::Abi::Scalar(ref scalar) = arg.layout.abi {
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if let layout::Int(i, signed) = scalar.value {
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if !signed && i.size().bits() == 32 {
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if let PassMode::Direct(ref mut attrs) = arg.mode {
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attrs.set(ArgAttribute::SExt);
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return;
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}
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}
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}
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}
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fn classify_ret_ty<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>,
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ret: &mut ArgType<'tcx>,
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offset: &mut Size) {
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if !ret.layout.is_aggregate() {
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ret.extend_integer_width_to(64);
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arg.extend_integer_width_to(bits);
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}
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fn bits_to_int_reg(bits: u64) -> Reg {
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if bits <= 8 {
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Reg::i8()
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} else if bits <= 16 {
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Reg::i16()
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} else if bits <= 32 {
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Reg::i32()
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} else {
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ret.make_indirect();
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*offset += cx.tcx.data_layout.pointer_size;
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Reg::i64()
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}
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}
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fn classify_arg_ty(cx: &CodegenCx, arg: &mut ArgType, offset: &mut Size) {
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let dl = &cx.tcx.data_layout;
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let size = arg.layout.size;
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let align = arg.layout.align.max(dl.i32_align).min(dl.i64_align);
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fn float_reg<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, ret: &ArgType<'tcx>, i: usize) -> Option<Reg> {
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match ret.layout.field(cx, i).abi {
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layout::Abi::Scalar(ref scalar) => match scalar.value {
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layout::F32 => Some(Reg::f32()),
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layout::F64 => Some(Reg::f64()),
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_ => None
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},
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_ => None
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}
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}
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if arg.layout.is_aggregate() {
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arg.cast_to(Uniform {
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unit: Reg::i64(),
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total: size
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});
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if !offset.is_abi_aligned(align) {
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arg.pad_with(Reg::i64());
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}
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} else {
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arg.extend_integer_width_to(64);
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fn classify_ret_ty<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, ret: &mut ArgType<'tcx>) {
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if !ret.layout.is_aggregate() {
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extend_integer_width_mips(ret, 64);
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return;
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}
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*offset = offset.abi_align(align) + size.abi_align(align);
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let size = ret.layout.size;
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let bits = size.bits();
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if bits <= 128 {
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// Unlike other architectures which return aggregates in registers, MIPS n64 limits the
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// use of float registers to structures (not unions) containing exactly one or two
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// float fields.
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if let layout::FieldPlacement::Arbitrary { .. } = ret.layout.fields {
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if ret.layout.fields.count() == 1 {
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if let Some(reg) = float_reg(cx, ret, 0) {
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ret.cast_to(reg);
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return;
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}
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} else if ret.layout.fields.count() == 2 {
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if let Some(reg0) = float_reg(cx, ret, 0) {
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if let Some(reg1) = float_reg(cx, ret, 1) {
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ret.cast_to(CastTarget::Pair(reg0, reg1));
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return;
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}
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}
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}
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}
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// Cast to a uniform int structure
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ret.cast_to(Uniform {
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unit: bits_to_int_reg(bits),
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total: size
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});
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} else {
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ret.make_indirect();
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}
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}
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fn classify_arg_ty<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, arg: &mut ArgType<'tcx>) {
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if !arg.layout.is_aggregate() {
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extend_integer_width_mips(arg, 64);
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return;
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}
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let dl = &cx.tcx.data_layout;
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let size = arg.layout.size;
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let mut prefix = [RegKind::Integer; 8];
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let mut prefix_index = 0;
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match arg.layout.fields {
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layout::FieldPlacement::Array { .. } => {
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// Arrays are passed indirectly
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arg.make_indirect();
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return;
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}
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layout::FieldPlacement::Union(_) => {
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// Unions and are always treated as a series of 64-bit integer chunks
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},
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layout::FieldPlacement::Arbitrary { .. } => {
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// Structures are split up into a series of 64-bit integer chunks, but any aligned
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// doubles not part of another aggregate are passed as floats.
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let mut last_offset = Size::from_bytes(0);
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for i in 0..arg.layout.fields.count() {
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let field = arg.layout.field(cx, i);
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let offset = arg.layout.fields.offset(i);
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// We only care about aligned doubles
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if let layout::Abi::Scalar(ref scalar) = field.abi {
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if let layout::F64 = scalar.value {
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if offset.is_abi_aligned(dl.f64_align) {
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// Skip over enough integers to cover [last_offset, offset)
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assert!(last_offset.is_abi_aligned(dl.f64_align));
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prefix_index += ((offset - last_offset).bits() / 64) as usize;
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if prefix_index >= prefix.len() {
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break;
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}
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prefix[prefix_index] = RegKind::Float;
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prefix_index += 1;
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last_offset = offset + Reg::f64().size;
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}
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}
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}
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}
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}
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};
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// Extract first 8 chunks as the prefix
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arg.cast_to(CastTarget::ChunkedPrefix {
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prefix: prefix,
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chunk: Size::from_bytes(8),
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total: size
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});
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}
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pub fn compute_abi_info<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, fty: &mut FnType<'tcx>) {
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let mut offset = Size::from_bytes(0);
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if !fty.ret.is_ignore() {
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classify_ret_ty(cx, &mut fty.ret, &mut offset);
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classify_ret_ty(cx, &mut fty.ret);
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}
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for arg in &mut fty.args {
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if arg.is_ignore() { continue; }
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classify_arg_ty(cx, arg, &mut offset);
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classify_arg_ty(cx, arg);
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}
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}
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