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Rollup merge of #110884 - korran:unaligned-scalar-mem, r=wesleywiser

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Support RISC-V unaligned-scalar-mem target feature

This adds `unaligned-scalar-mem` as an allowed RISC-V target feature. Some RISC-V cores support unaligned access to memory without trapping. On such cores, the compiler could significantly improve code-size and performance when using functions like core::ptr::read_unaligned<u32> by emitting a single load or store instruction with an unaligned address, rather than a long sequence of byte load/store/bitmanip instructions.

Enabling the `unaligned-scalar-mem` target feature allows LLVM to do this optimization.

Fixes #110883
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Dylan DPC 2023-05-18 10:52:33 +05:30 committed by GitHub
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compiler/rustc_codegen_ssa/src/target_features.rs
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@ -250,6 +250,7 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("f", Some(sym::riscv_target_feature)), ("f", Some(sym::riscv_target_feature)),
("m", Some(sym::riscv_target_feature)), ("m", Some(sym::riscv_target_feature)),
("relax", Some(sym::riscv_target_feature)), ("relax", Some(sym::riscv_target_feature)),
("unaligned-scalar-mem", Some(sym::riscv_target_feature)),
("v", Some(sym::riscv_target_feature)), ("v", Some(sym::riscv_target_feature)),
("zba", Some(sym::riscv_target_feature)), ("zba", Some(sym::riscv_target_feature)),
("zbb", Some(sym::riscv_target_feature)), ("zbb", Some(sym::riscv_target_feature)),