From 3e9b993925477a3c4506b02373c75605fe17c2f0 Mon Sep 17 00:00:00 2001 From: Steve Klabnik Date: Wed, 30 Sep 2015 13:24:28 -0400 Subject: [PATCH] Clarify logic instead of using 'vice versa' Fixes #28166 --- src/libcore/cmp.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/libcore/cmp.rs b/src/libcore/cmp.rs index 3344d7ea5d7..fa1f4727bc0 100644 --- a/src/libcore/cmp.rs +++ b/src/libcore/cmp.rs @@ -218,7 +218,7 @@ impl PartialOrd for Ordering { /// /// The comparison must satisfy, for all `a`, `b` and `c`: /// -/// - antisymmetry: if `a < b` then `!(a > b)` and vice versa; and +/// - antisymmetry: if `a < b` then `!(a > b)`, as well as `a > b` implying `!(a < b)`; and /// - transitivity: `a < b` and `b < c` implies `a < c`. The same must hold for both `==` and `>`. /// /// Note that these requirements mean that the trait itself must be implemented symmetrically and