Rollup merge of #72439 - westernmagic:master, r=Amanieu
NVPTX support for new asm! This PR implements the new `asm!` syntax for the `nvptx64-nvidia-cuda` target. r? @Amanieu
This commit is contained in:
Ralf Jung
GitHub
commit
37894559ab
@ -468,12 +468,17 @@ Here is the list of currently supported register classes:
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| ARM | `qreg` | `q[0-15]` | `w` |
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| ARM | `qreg_low8` | `q[0-7]` | `t` |
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| ARM | `qreg_low4` | `q[0-3]` | `x` |
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| NVPTX | `reg16` | None\* | `h` |
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| NVPTX | `reg32` | None\* | `r` |
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| NVPTX | `reg64` | None\* | `l` |
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| RISC-V | `reg` | `x1`, `x[5-7]`, `x[9-15]`, `x[16-31]` (non-RV32E) | `r` |
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| RISC-V | `freg` | `f[0-31]` | `f` |
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> **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
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>
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> Note #2: On x86-64 the high byte registers (e.g. `ah`) are only available when used as an explicit register. Specifying the `reg_byte` register class for an operand will always allocate a low byte register.
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>
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> Note #3: NVPTX doesn't have a fixed register set, so named registers are not supported.
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Additional register classes may be added in the future based on demand (e.g. MMX, x87, etc).
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@ -495,6 +500,9 @@ Each register class has constraints on which value types they can be used with.
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| ARM | `sreg` | `vfp2` | `i32`, `f32` |
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| ARM | `dreg` | `vfp2` | `i64`, `f64`, `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2` |
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| ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
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| NVPTX | `reg16` | None | `i8`, `i16` |
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| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
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| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
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| RISC-V32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
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| RISC-V64 | `reg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
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| RISC-V | `freg` | `f` | `f32` |
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@ -610,6 +618,9 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
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| ARM | `dreg` | None | `d0` | `P` |
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| ARM | `qreg` | None | `q0` | `q` |
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| ARM | `qreg` | `e` / `f` | `d0` / `d1` | `e` / `f` |
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| NVPTX | `reg16` | None | `rs0` | None |
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| NVPTX | `reg32` | None | `r0` | None |
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| NVPTX | `reg64` | None | `rd0` | None |
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| RISC-V | `reg` | None | `x1` | None |
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| RISC-V | `freg` | None | `f0` | None |
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@ -254,6 +254,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
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]);
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
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InlineAsmArch::Nvptx64 => {}
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}
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}
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if !options.contains(InlineAsmOptions::NOMEM) {
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@ -410,6 +411,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String {
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
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InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
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InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",
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InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
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@ -452,6 +456,7 @@ fn modifier_to_llvm(
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modifier
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}
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}
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InlineAsmRegClass::Nvptx(_) => None,
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InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
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| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
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InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
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@ -502,6 +507,9 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
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cx.type_vector(cx.type_i64(), 2)
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}
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
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InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
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InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
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@ -60,6 +60,7 @@ macro_rules! def_regs {
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#error = [$($bad_reg:literal),+] => $error:literal,
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)*
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}) => {
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#[allow(unreachable_code)]
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#[derive(Copy, Clone, RustcEncodable, RustcDecodable, Debug, Eq, PartialEq, Hash, HashStable_Generic)]
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#[allow(non_camel_case_types)]
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pub enum $arch_reg {
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@ -102,19 +103,20 @@ macro_rules! def_regs {
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pub(super) fn fill_reg_map(
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_arch: super::InlineAsmArch,
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mut _has_feature: impl FnMut(&str) -> bool,
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map: &mut rustc_data_structures::fx::FxHashMap<
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_map: &mut rustc_data_structures::fx::FxHashMap<
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super::InlineAsmRegClass,
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rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,
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>,
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) {
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#[allow(unused_imports)]
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use super::{InlineAsmReg, InlineAsmRegClass};
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$(
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if $($filter(_arch, &mut _has_feature, true).is_ok() &&)? true {
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if let Some(set) = map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
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if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
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set.insert(InlineAsmReg::$arch($arch_reg::$reg));
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}
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$(
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if let Some(set) = map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {
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if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {
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set.insert(InlineAsmReg::$arch($arch_reg::$reg));
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}
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)*
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@ -146,11 +148,13 @@ macro_rules! types {
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mod aarch64;
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mod arm;
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mod nvptx;
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mod riscv;
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mod x86;
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pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
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pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
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pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
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pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
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pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
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@ -162,6 +166,7 @@ pub enum InlineAsmArch {
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AArch64,
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RiscV32,
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RiscV64,
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Nvptx64,
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}
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impl FromStr for InlineAsmArch {
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@ -175,6 +180,7 @@ impl FromStr for InlineAsmArch {
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"aarch64" => Ok(Self::AArch64),
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"riscv32" => Ok(Self::RiscV32),
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"riscv64" => Ok(Self::RiscV64),
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"nvptx64" => Ok(Self::Nvptx64),
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_ => Err(()),
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}
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}
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@ -196,6 +202,7 @@ pub enum InlineAsmReg {
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Arm(ArmInlineAsmReg),
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AArch64(AArch64InlineAsmReg),
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RiscV(RiscVInlineAsmReg),
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Nvptx(NvptxInlineAsmReg),
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}
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impl InlineAsmReg {
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@ -236,6 +243,9 @@ impl InlineAsmReg {
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, &name)?)
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}
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InlineAsmArch::Nvptx64 => {
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Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, &name)?)
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}
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})
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}
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@ -281,6 +291,7 @@ pub enum InlineAsmRegClass {
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Arm(ArmInlineAsmRegClass),
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AArch64(AArch64InlineAsmRegClass),
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RiscV(RiscVInlineAsmRegClass),
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Nvptx(NvptxInlineAsmRegClass),
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}
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impl InlineAsmRegClass {
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@ -290,6 +301,7 @@ impl InlineAsmRegClass {
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Self::Arm(r) => r.name(),
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Self::AArch64(r) => r.name(),
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Self::RiscV(r) => r.name(),
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Self::Nvptx(r) => r.name(),
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}
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}
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@ -302,6 +314,7 @@ impl InlineAsmRegClass {
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Self::Arm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Arm),
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Self::AArch64(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::AArch64),
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Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
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Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
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}
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}
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@ -321,6 +334,7 @@ impl InlineAsmRegClass {
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Self::Arm(r) => r.suggest_modifier(arch, ty),
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Self::AArch64(r) => r.suggest_modifier(arch, ty),
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Self::RiscV(r) => r.suggest_modifier(arch, ty),
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Self::Nvptx(r) => r.suggest_modifier(arch, ty),
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}
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}
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@ -336,6 +350,7 @@ impl InlineAsmRegClass {
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Self::Arm(r) => r.default_modifier(arch),
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Self::AArch64(r) => r.default_modifier(arch),
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Self::RiscV(r) => r.default_modifier(arch),
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Self::Nvptx(r) => r.default_modifier(arch),
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}
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}
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@ -350,6 +365,7 @@ impl InlineAsmRegClass {
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Self::Arm(r) => r.supported_types(arch),
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Self::AArch64(r) => r.supported_types(arch),
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Self::RiscV(r) => r.supported_types(arch),
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Self::Nvptx(r) => r.supported_types(arch),
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}
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}
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@ -367,6 +383,7 @@ impl InlineAsmRegClass {
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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Self::RiscV(RiscVInlineAsmRegClass::parse(arch, name)?)
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}
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InlineAsmArch::Nvptx64 => Self::Nvptx(NvptxInlineAsmRegClass::parse(arch, name)?),
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})
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})
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}
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@ -379,6 +396,7 @@ impl InlineAsmRegClass {
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Self::Arm(r) => r.valid_modifiers(arch),
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Self::AArch64(r) => r.valid_modifiers(arch),
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Self::RiscV(r) => r.valid_modifiers(arch),
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Self::Nvptx(r) => r.valid_modifiers(arch),
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}
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}
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}
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@ -518,5 +536,10 @@ pub fn allocatable_registers(
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riscv::fill_reg_map(arch, has_feature, &mut map);
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map
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}
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InlineAsmArch::Nvptx64 => {
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let mut map = nvptx::regclass_map();
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nvptx::fill_reg_map(arch, has_feature, &mut map);
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map
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}
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}
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}
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49
src/librustc_target/asm/nvptx.rs
Normal file
49
src/librustc_target/asm/nvptx.rs
Normal file
@ -0,0 +1,49 @@
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use super::{InlineAsmArch, InlineAsmType};
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use rustc_macros::HashStable_Generic;
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def_reg_class! {
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Nvptx NvptxInlineAsmRegClass {
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reg16,
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reg32,
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reg64,
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}
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}
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impl NvptxInlineAsmRegClass {
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pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] {
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&[]
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}
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pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
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None
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}
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pub fn suggest_modifier(
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self,
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_arch: InlineAsmArch,
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_ty: InlineAsmType,
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) -> Option<(char, &'static str)> {
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None
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}
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pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
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None
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}
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pub fn supported_types(
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self,
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_arch: InlineAsmArch,
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) -> &'static [(InlineAsmType, Option<&'static str>)] {
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match self {
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Self::reg16 => types! { _: I8, I16; },
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Self::reg32 => types! { _: I8, I16, I32, F32; },
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Self::reg64 => types! { _: I8, I16, I32, F32, I64, F64; },
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}
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}
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}
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def_regs! {
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// Registers in PTX are declared in the assembly.
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// There are no predefined registers that one can use.
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Nvptx NvptxInlineAsmReg NvptxInlineAsmRegClass {}
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}
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133
src/test/assembly/asm/nvptx-types.rs
Normal file
133
src/test/assembly/asm/nvptx-types.rs
Normal file
@ -0,0 +1,133 @@
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// no-system-llvm
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// assembly-output: emit-asm
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// compile-flags: --target nvptx64-nvidia-cuda
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// compile-flags: --crate-type cdylib
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#![feature(no_core, lang_items, rustc_attrs)]
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#![no_core]
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#[rustc_builtin_macro]
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macro_rules! asm {
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() => {};
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}
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#[rustc_builtin_macro]
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macro_rules! concat {
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() => {};
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}
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#[lang = "sized"]
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trait Sized {}
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#[lang = "copy"]
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trait Copy {}
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type ptr = *mut u8;
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impl Copy for i8 {}
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impl Copy for i16 {}
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impl Copy for i32 {}
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impl Copy for f32 {}
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impl Copy for i64 {}
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impl Copy for f64 {}
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impl Copy for ptr {}
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// NVPTX does not support static variables
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#[no_mangle]
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fn extern_func() {}
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// CHECK-LABEL: .visible .func sym_fn()
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// CHECK: // begin inline asm
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// CHECK: call extern_func;
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// CHECK: // end inline asm
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#[no_mangle]
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pub unsafe fn sym_fn() {
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asm!("call {};", sym extern_func);
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}
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macro_rules! check {
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($func:ident $ty:ident $class:ident $mov:literal) => {
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#[no_mangle]
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pub unsafe fn $func(x: $ty) -> $ty {
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let y;
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asm!(concat!($mov, " {}, {};"), out($class) y, in($class) x);
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y
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}
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};
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}
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// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg16_i8
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// CHECK: // begin inline asm
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// CHECK: mov.i16 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
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// CHECK: // end inline asm
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check!(reg16_i8 i8 reg16 "mov.i16");
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// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg16_i16
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// CHECK: // begin inline asm
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// CHECK: mov.i16 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
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// CHECK: // end inline asm
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check!(reg16_i16 i16 reg16 "mov.i16");
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// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg32_i8
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// CHECK: // begin inline asm
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// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
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// CHECK: // end inline asm
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check!(reg32_i8 i8 reg32 "mov.i32");
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// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg32_i16
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// CHECK: // begin inline asm
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// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
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// CHECK: // end inline asm
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check!(reg32_i16 i16 reg32 "mov.i32");
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// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg32_i32
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// CHECK: // begin inline asm
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// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
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// CHECK: // end inline asm
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check!(reg32_i32 i32 reg32 "mov.i32");
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// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg32_f32
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// CHECK: // begin inline asm
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// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
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// CHECK: // end inline asm
|
||||
check!(reg32_f32 f32 reg32 "mov.i32");
|
||||
|
||||
// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg64_i8
|
||||
// CHECK: // begin inline asm
|
||||
// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
|
||||
// CHECK: // end inline asm
|
||||
check!(reg64_i8 i8 reg64 "mov.i64");
|
||||
|
||||
// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg64_i16
|
||||
// CHECK: // begin inline asm
|
||||
// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
|
||||
// CHECK: // end inline asm
|
||||
check!(reg64_i16 i16 reg64 "mov.i64");
|
||||
|
||||
// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg64_i32
|
||||
// CHECK: // begin inline asm
|
||||
// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
|
||||
// CHECK: // end inline asm
|
||||
check!(reg64_i32 i32 reg64 "mov.i64");
|
||||
|
||||
// CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg64_f32
|
||||
// CHECK: // begin inline asm
|
||||
// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
|
||||
// CHECK: // end inline asm
|
||||
check!(reg64_f32 f32 reg64 "mov.i64");
|
||||
|
||||
// CHECK-LABEL: .visible .func (.param .b64 func_retval0) reg64_i64
|
||||
// CHECK: // begin inline asm
|
||||
// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
|
||||
// CHECK: // end inline asm
|
||||
check!(reg64_i64 i64 reg64 "mov.i64");
|
||||
|
||||
// CHECK-LABEL: .visible .func (.param .b64 func_retval0) reg64_f64
|
||||
// CHECK: // begin inline asm
|
||||
// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
|
||||
// CHECK: // end inline asm
|
||||
check!(reg64_f64 f64 reg64 "mov.i64");
|
||||
|
||||
// CHECK-LABEL: .visible .func (.param .b64 func_retval0) reg64_ptr
|
||||
// CHECK: // begin inline asm
|
||||
// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
|
||||
// CHECK: // end inline asm
|
||||
check!(reg64_ptr ptr reg64 "mov.i64");
|
||||
Loading…
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Reference in New Issue
Block a user