Merge pull request #1490 from folkertdev/add-llvm-x86-crc32
add all `llvm.x86.sse42.crc32.*.*` intrinsics
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commit
2df34f9091
@ -210,6 +210,21 @@ fn rust_call_abi() {
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#[allow(improper_ctypes_definitions)]
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extern "C" fn foo(_a: I64X2) {}
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#[cfg(target_arch = "x86_64")]
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#[target_feature(enable = "sse4.2")]
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#[cfg(not(jit))]
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unsafe fn test_crc32() {
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assert!(is_x86_feature_detected!("sse4.2"));
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let a = 42u32;
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let b = 0xdeadbeefu64;
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assert_eq!(_mm_crc32_u8(a, b as u8), 4135334616);
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assert_eq!(_mm_crc32_u16(a, b as u16), 1200687288);
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assert_eq!(_mm_crc32_u32(a, b as u32), 2543798776);
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assert_eq!(_mm_crc32_u64(a as u64, b as u64), 241952147);
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}
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#[cfg(target_arch = "x86_64")]
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#[target_feature(enable = "sse2")]
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unsafe fn test_simd() {
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@ -249,6 +264,9 @@ unsafe fn test_simd() {
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#[rustfmt::skip]
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let mask1 = _mm_movemask_epi8(dbg!(_mm_setr_epi8(255u8 as i8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)));
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assert_eq!(mask1, 1);
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#[cfg(not(jit))]
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test_crc32();
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}
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#[cfg(target_arch = "x86_64")]
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@ -847,16 +847,27 @@ fn select4(
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}
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}
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"llvm.x86.sse42.crc32.32.32" => {
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"llvm.x86.sse42.crc32.32.8"
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| "llvm.x86.sse42.crc32.32.16"
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| "llvm.x86.sse42.crc32.32.32"
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| "llvm.x86.sse42.crc32.64.64" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#ig_expand=1419&text=_mm_crc32_u32
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intrinsic_args!(fx, args => (crc, v); intrinsic);
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let crc = crc.load_scalar(fx);
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let v = v.load_scalar(fx);
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let asm = match intrinsic {
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"llvm.x86.sse42.crc32.32.8" => "crc32 eax, dl",
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"llvm.x86.sse42.crc32.32.16" => "crc32 eax, dx",
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"llvm.x86.sse42.crc32.32.32" => "crc32 eax, edx",
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"llvm.x86.sse42.crc32.64.64" => "crc32 rax, rdx",
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_ => unreachable!(),
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};
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codegen_inline_asm_inner(
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fx,
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&[InlineAsmTemplatePiece::String("crc32 eax, edx".to_string())],
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&[InlineAsmTemplatePiece::String(asm.to_string())],
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&[
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CInlineAsmOperand::InOut {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax)),
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