mikros/rust
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Rollup merge of #131807 - beetrees:riscv-target-abi, r=workingjubilee

Browse Source 
Always specify `llvm_abiname` for RISC-V targets

For RISC-V targets, when `llvm_abiname` is not specified LLVM will infer the ABI from the target features, causing #116344 to occur. This PR adds the correct `llvm_abiname` to all RISC-V targets where it is missing (which are all soft-float targets), and adds a test to prevent future RISC-V targets from accidentally omitting `llvm_abiname`. The only affect of this PR is that `-Ctarget-feature=+f` (or similar) will no longer affect the ABI on the modified targets.

<!-- homu-ignore:start -->
r? `@RalfJung`
<!--- homu-ignore:end -->
This commit is contained in:
Jubilee 2024-10-21 20:32:01 -07:00 committed by GitHub
commit 1b24c6fc14
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
16 changed files with 71 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
compiler/rustc_target/src/spec/targets/riscv32i_unknown_none_elf.rs
View File

@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
max_atomic_width: Some(32),
atomic_cas: false,
features: "+forced-atomics".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,

1
compiler/rustc_target/src/spec/targets/riscv32im_risc0_zkvm_elf.rs
View File

@ -29,6 +29,7 @@ pub(crate) fn target() -> Target {
atomic_cas: true,
features: "+m".into(),
llvm_abiname: "ilp32".into(),
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,

1
compiler/rustc_target/src/spec/targets/riscv32im_unknown_none_elf.rs
View File

@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
max_atomic_width: Some(32),
atomic_cas: false,
features: "+m,+forced-atomics".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,

1
compiler/rustc_target/src/spec/targets/riscv32ima_unknown_none_elf.rs
View File

@ -19,6 +19,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+a".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,

1
compiler/rustc_target/src/spec/targets/riscv32imac_esp_espidf.rs
View File

@ -27,6 +27,7 @@ pub(crate) fn target() -> Target {
atomic_cas: true,
features: "+m,+a,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,

1
compiler/rustc_target/src/spec/targets/riscv32imac_unknown_none_elf.rs
View File

@ -19,6 +19,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+a,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,

1
compiler/rustc_target/src/spec/targets/riscv32imac_unknown_nuttx_elf.rs
View File

@ -21,6 +21,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+a,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Unwind,
relocation_model: RelocModel::Static,
..Default::default()

1
compiler/rustc_target/src/spec/targets/riscv32imac_unknown_xous_elf.rs
View File

@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+a,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Unwind,
relocation_model: RelocModel::Static,
..Default::default()

1
compiler/rustc_target/src/spec/targets/riscv32imc_esp_espidf.rs
View File

@ -30,6 +30,7 @@ pub(crate) fn target() -> Target {
atomic_cas: true,
features: "+m,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,

1
compiler/rustc_target/src/spec/targets/riscv32imc_unknown_none_elf.rs
View File

@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
max_atomic_width: Some(32),
atomic_cas: false,
features: "+m,+c,+forced-atomics".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,

1
compiler/rustc_target/src/spec/targets/riscv32imc_unknown_nuttx_elf.rs
View File

@ -21,6 +21,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: "+m,+c".into(),
llvm_abiname: "ilp32".into(),
panic_strategy: PanicStrategy::Unwind,
relocation_model: RelocModel::Static,
..Default::default()

1
compiler/rustc_target/src/spec/targets/riscv64imac_unknown_none_elf.rs
View File

@ -22,6 +22,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv64".into(),
max_atomic_width: Some(64),
features: "+m,+a,+c".into(),
llvm_abiname: "lp64".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
code_model: Some(CodeModel::Medium),

1
compiler/rustc_target/src/spec/targets/riscv64imac_unknown_nuttx_elf.rs
View File

@ -24,6 +24,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv64".into(),
max_atomic_width: Some(64),
features: "+m,+a,+c".into(),
llvm_abiname: "lp64".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
code_model: Some(CodeModel::Medium),

11
compiler/rustc_target/src/spec/tests/tests_impl.rs
View File

@ -152,6 +152,17 @@ fn check_consistency(&self) {
if self.crt_static_default || self.crt_static_allows_dylibs {
assert!(self.crt_static_respected);
}
// Check that RISC-V targets always specify which ABI they use.
match &*self.arch {
"riscv32" => {
assert_matches!(&*self.llvm_abiname, "ilp32" | "ilp32f" | "ilp32d" | "ilp32e")
}
"riscv64" => {
assert_matches!(&*self.llvm_abiname, "lp64" | "lp64f" | "lp64d" | "lp64q")
}
_ => {}
}
}
// Add your target to the whitelist if it has `std` library

46
tests/assembly/riscv-soft-abi-with-float-features.rs Normal file
View File

@ -0,0 +1,46 @@
//@ assembly-output: emit-asm
//@ compile-flags: --target riscv64imac-unknown-none-elf -Ctarget-feature=+f,+d
//@ needs-llvm-components: riscv
#![feature(no_core, lang_items, f16)]
#![crate_type = "lib"]
#![no_core]
#[lang = "sized"]
trait Sized {}
#[lang = "copy"]
trait Copy {}
impl Copy for f16 {}
impl Copy for f32 {}
impl Copy for f64 {}
// This test checks that the floats are all returned in `a0` as required by the `lp64` ABI.
// CHECK-LABEL: read_f16
#[no_mangle]
pub extern "C" fn read_f16(x: &f16) -> f16 {
// CHECK: lh a0, 0(a0)
// CHECK-NEXT: lui a1, 1048560
// CHECK-NEXT: or a0, a0, a1
// CHECK-NEXT: ret
*x
}
// CHECK-LABEL: read_f32
#[no_mangle]
pub extern "C" fn read_f32(x: &f32) -> f32 {
// CHECK: flw fa5, 0(a0)
// CHECK-NEXT: fmv.x.w a0, fa5
// CHECK-NEXT: ret
*x
}
// CHECK-LABEL: read_f64
#[no_mangle]
pub extern "C" fn read_f64(x: &f64) -> f64 {
// CHECK: ld a0, 0(a0)
// CHECK-NEXT: ret
*x
}

2
tests/codegen/riscv-target-abi.rs
View File

@ -10,7 +10,7 @@
//@[riscv32imac] compile-flags: --target=riscv32imac-unknown-none-elf
//@[riscv32imac] needs-llvm-components: riscv
// riscv32imac-NOT: !"target-abi"
// riscv32imac: !{i32 1, !"target-abi", !"ilp32"}
#![feature(no_core, lang_items)]
#![crate_type = "lib"]