Add riscv32 imafc bare metal target
- riscv32imac-unknown-none-elf - Add platform support docs for rv32
This commit is contained in:
Scott Mabin
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1670ff64bf
commit
1a7b610da3
@ -1637,6 +1637,7 @@ supported_targets! {
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("riscv32imc-esp-espidf", riscv32imc_esp_espidf),
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("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
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("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
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("riscv32imafc-unknown-none-elf", riscv32imafc_unknown_none_elf),
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("riscv32imac-unknown-xous-elf", riscv32imac_unknown_xous_elf),
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("riscv32gc-unknown-linux-gnu", riscv32gc_unknown_linux_gnu),
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("riscv32gc-unknown-linux-musl", riscv32gc_unknown_linux_musl),
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@ -0,0 +1,24 @@
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use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};
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pub fn target() -> Target {
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Target {
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data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
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llvm_target: "riscv32".into(),
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pointer_width: 32,
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arch: "riscv32".into(),
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options: TargetOptions {
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linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
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linker: Some("rust-lld".into()),
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cpu: "generic-rv32".into(),
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max_atomic_width: Some(32),
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llvm_abiname: "ilp32f".into(),
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features: "+m,+a,+c,+f".into(),
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panic_strategy: PanicStrategy::Abort,
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relocation_model: RelocModel::Static,
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emit_debug_gdb_scripts: false,
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eh_frame_header: false,
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..Default::default()
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},
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}
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}
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@ -95,6 +95,7 @@ ENV TARGETS=$TARGETS,thumbv8m.main-none-eabihf
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ENV TARGETS=$TARGETS,riscv32i-unknown-none-elf
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ENV TARGETS=$TARGETS,riscv32imc-unknown-none-elf
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ENV TARGETS=$TARGETS,riscv32imac-unknown-none-elf
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ENV TARGETS=$TARGETS,riscv32imafc-unknown-none-elf
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ENV TARGETS=$TARGETS,riscv64imac-unknown-none-elf
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ENV TARGETS=$TARGETS,riscv64gc-unknown-none-elf
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ENV TARGETS=$TARGETS,armebv7r-none-eabi
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@ -45,6 +45,7 @@
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- [nvptx64-nvidia-cuda](platform-support/nvptx64-nvidia-cuda.md)
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- [powerpc64-ibm-aix](platform-support/aix.md)
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- [riscv32imac-unknown-xous-elf](platform-support/riscv32imac-unknown-xous-elf.md)
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- [riscv32*-unknown-none-elf](platform-support/riscv32imac-unknown-none-elf.md)
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- [sparc-unknown-none-elf](./platform-support/sparc-unknown-none-elf.md)
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- [*-pc-windows-gnullvm](platform-support/pc-windows-gnullvm.md)
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- [\*-nto-qnx-\*](platform-support/nto-qnx.md)
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@ -159,9 +159,9 @@ target | std | notes
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[`loongarch64-unknown-none`](platform-support/loongarch-none.md) | * | | LoongArch64 Bare-metal (LP64D ABI)
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[`loongarch64-unknown-none-softfloat`](platform-support/loongarch-none.md) | * | | LoongArch64 Bare-metal (LP64S ABI)
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[`nvptx64-nvidia-cuda`](platform-support/nvptx64-nvidia-cuda.md) | * | --emit=asm generates PTX code that [runs on NVIDIA GPUs]
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`riscv32i-unknown-none-elf` | * | Bare RISC-V (RV32I ISA)
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`riscv32imac-unknown-none-elf` | * | Bare RISC-V (RV32IMAC ISA)
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`riscv32imc-unknown-none-elf` | * | Bare RISC-V (RV32IMC ISA)
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[`riscv32imac-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAC ISA)
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[`riscv32i-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32I ISA)
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[`riscv32imc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMC ISA)
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`riscv64gc-unknown-none-elf` | * | Bare RISC-V (RV64IMAFDC ISA)
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`riscv64imac-unknown-none-elf` | * | Bare RISC-V (RV64IMAC ISA)
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`sparc64-unknown-linux-gnu` | ✓ | SPARC Linux (kernel 4.4, glibc 2.23)
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@ -314,7 +314,8 @@ target | std | host | notes
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[`powerpc64-ibm-aix`](platform-support/aix.md) | ? | | 64-bit AIX (7.2 and newer)
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`riscv32gc-unknown-linux-gnu` | | | RISC-V Linux (kernel 5.4, glibc 2.33)
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`riscv32gc-unknown-linux-musl` | | | RISC-V Linux (kernel 5.4, musl + RISCV32 support patches)
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`riscv32im-unknown-none-elf` | * | | Bare RISC-V (RV32IM ISA)
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[`riscv32imafc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAFC ISA)
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[`riscv32im-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | | Bare RISC-V (RV32IM ISA)
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[`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? | | RISC-V Xous (RV32IMAC ISA)
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[`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
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[`riscv32imac-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
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@ -0,0 +1 @@
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riscv32imac-unknown-none-elf.md
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@ -0,0 +1 @@
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riscv32imac-unknown-none-elf.md
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@ -0,0 +1,34 @@
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# `riscv32{i,im,imc,imac,imafc}-unknown-none-elf`
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**Tier: 2/3**
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Bare-metal target for RISC-V CPUs with the RV32I, RV32IM, RV32IMC, RV32IMAFC and RV32IMAC ISAs.
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## Target maintainers
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* Rust Embedded Working Group, [RISC-V team](https://github.com/rust-embedded/wg#the-risc-v-team)
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## Requirements
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The target is cross-compiled, and uses static linking. No external toolchain
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is required and the default `rust-lld` linker works, but you must specify
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a linker script. The [`riscv-rt`] crate provides a suitable one. The
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[`riscv-rust-quickstart`] repository gives an example of an RV32 project.
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[`riscv-rt`]: https://crates.io/crates/riscv-rt
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[`riscv-rust-quickstart`]: https://github.com/riscv-rust/riscv-rust-quickstart
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## Building the target
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This target is included in Rust and can be installed via `rustup`.
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## Testing
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This is a cross-compiled no-std target, which must be run either in a simulator
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or by programming them onto suitable hardware. It is not possible to run the
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Rust testsuite on this target.
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## Cross-compilation toolchains and C code
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This target supports C code. If interlinking with C or C++, you may need to use
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riscv64-unknown-elf-gcc as a linker instead of rust-lld.
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@ -0,0 +1 @@
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riscv32imac-unknown-none-elf.md
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@ -0,0 +1 @@
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riscv32imac-unknown-none-elf.md
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@ -124,6 +124,7 @@ static TARGETS: &[&str] = &[
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"riscv32im-unknown-none-elf",
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"riscv32imc-unknown-none-elf",
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"riscv32imac-unknown-none-elf",
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"riscv32imafc-unknown-none-elf",
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"riscv32gc-unknown-linux-gnu",
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"riscv64imac-unknown-none-elf",
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"riscv64gc-unknown-hermit",
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