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Remove LLVM ARM bug workaround

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This memset was inserted as a workaround to Rust issue #34427, which was
an LLVM bug that apparently no longer manifests.
This commit is contained in:
Michael Benfield 2022-08-24 05:26:04 +00:00
parent 25ea5a36c6
commit 12a9914a86
1 changed files with 0 additions and 11 deletions
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11
compiler/rustc_codegen_ssa/src/mir/place.rs
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@ -4,7 +4,6 @@
use crate::common::IntPredicate;
use crate::glue;
use crate::traits::*;
use crate::MemFlags;
use rustc_middle::mir;
use rustc_middle::mir::tcx::PlaceTy;
@ -343,16 +342,6 @@ pub fn codegen_set_discr<Bx: BuilderMethods<'a, 'tcx, Value = V>>(
..
} => {
if variant_index != dataful_variant {
if bx.cx().sess().target.arch == "arm"
|| bx.cx().sess().target.arch == "aarch64"
{
// FIXME(#34427): as workaround for LLVM bug on ARM,
// use memset of 0 before assigning niche value.
let fill_byte = bx.cx().const_u8(0);
let size = bx.cx().const_usize(self.layout.size.bytes());
bx.memset(self.llval, fill_byte, size, self.align, MemFlags::empty());
}
let niche = self.project_field(bx, tag_field);
let niche_llty = bx.cx().immediate_backend_type(niche.layout);
let niche_value = variant_index.as_u32() - niche_variants.start().as_u32();