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Add no_std Xtensa targets support

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This commit is contained in:
Sergio Gasquez 2024-05-14 17:16:59 +02:00 committed by Scott Mabin
parent e823288c35
commit 11f70d78f5
11 changed files with 138 additions and 2 deletions
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1
compiler/rustc_target/src/spec/base/mod.rs
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@ -35,3 +35,4 @@
pub(crate) mod windows_msvc;
pub(crate) mod windows_uwp_gnu;
pub(crate) mod windows_uwp_msvc;
pub(crate) mod xtensa;

17
compiler/rustc_target/src/spec/base/xtensa.rs Normal file
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@ -0,0 +1,17 @@
use crate::abi::Endian;
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, TargetOptions};
pub fn opts() -> TargetOptions {
TargetOptions {
os: "none".into(),
endian: Endian::Little,
c_int_width: "32".into(),
linker_flavor: LinkerFlavor::Gnu(Cc::Yes, Lld::No),
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
atomic_cas: false,
..Default::default()
}
}

4
compiler/rustc_target/src/spec/mod.rs
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@ -1766,6 +1766,10 @@ fn $module() {
("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda),
("xtensa-esp32-none-elf", xtensa_esp32_none_elf),
("xtensa-esp32s2-none-elf", xtensa_esp32s2_none_elf),
("xtensa-esp32s3-none-elf", xtensa_esp32s3_none_elf),
("i686-wrs-vxworks", i686_wrs_vxworks),
("x86_64-wrs-vxworks", x86_64_wrs_vxworks),
("armv7-wrs-vxworks-eabihf", armv7_wrs_vxworks_eabihf),

24
compiler/rustc_target/src/spec/targets/xtensa_esp32_none_elf.rs Normal file
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@ -0,0 +1,24 @@
use crate::spec::{base::xtensa, Target, TargetOptions};
pub fn target() -> Target {
Target {
llvm_target: "xtensa-none-elf".into(),
pointer_width: 32,
data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
arch: "xtensa".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Xtensa ESP32".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
options: TargetOptions {
cpu: "esp32".into(),
linker: Some("xtensa-esp32-elf-gcc".into()),
max_atomic_width: Some(32),
atomic_cas: true,
..xtensa::opts()
},
}
}

23
compiler/rustc_target/src/spec/targets/xtensa_esp32s2_none_elf.rs Normal file
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@ -0,0 +1,23 @@
use crate::spec::{base::xtensa, Target, TargetOptions};
pub fn target() -> Target {
Target {
llvm_target: "xtensa-none-elf".into(),
pointer_width: 32,
data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
arch: "xtensa".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Xtensa ESP32-S2".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
options: TargetOptions {
cpu: "esp32-s2".into(),
linker: Some("xtensa-esp32s2-elf-gcc".into()),
max_atomic_width: Some(32),
..xtensa::opts()
},
}
}

24
compiler/rustc_target/src/spec/targets/xtensa_esp32s3_none_elf.rs Normal file
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@ -0,0 +1,24 @@
use crate::spec::{base::xtensa, Target, TargetOptions};
pub fn target() -> Target {
Target {
llvm_target: "xtensa-none-elf".into(),
pointer_width: 32,
data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
arch: "xtensa".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Xtensa ESP32-S3".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
options: TargetOptions {
cpu: "esp32-s3".into(),
linker: Some("xtensa-esp32s3-elf-gcc".into()),
max_atomic_width: Some(32),
atomic_cas: true,
..xtensa::opts()
},
}
}

3
src/doc/rustc/src/platform-support.md
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@ -383,5 +383,8 @@ target | std | host | notes
`x86_64-wrs-vxworks` | ? | |
[`x86_64h-apple-darwin`](platform-support/x86_64h-apple-darwin.md) | ✓ | ✓ | macOS with late-gen Intel (at least Haswell)
[`x86_64-unknown-linux-none`](platform-support/x86_64-unknown-linux-none.md) | * | | 64-bit Linux with no libc
`xtensa-esp32-none-elf` | | | Xtensa ESP32
`xtensa-esp32s2-none-elf` | | | Xtensa ESP32-S2
`xtensa-esp32s3-none-elf` | | | Xtensa ESP32-S3
[runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets

25
src/doc/rustc/src/platform-support/xtensa.md Normal file
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@ -0,0 +1,25 @@
# `xtensa-*`
**Tier: 3**
Targets for Xtensa CPUs.
## Target maintainers
- Scott Mabin [@MabezDev](https://github.com/MabezDev)
- Sergio Gasquez [@SergioGasquez](https://github.com/SergioGasquez)
## Requirements
The target names follow this format: `xtensa-$CPU`, where `$CPU` specifies the target chip. The following targets are currently defined:
| Target name | Target CPU(s) |
| ------------------------- | --------------------------------------------------------------- |
| `xtensa-esp32-none-elf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) |
| `xtensa-esp32s2-none-elf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) |
| `xtensa-esp32s3-none-elf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) |
## Building the target
The targets can be built by installing the [Xtensa enabled Rust channel](https://github.com/esp-rs/rust/). See instructions in the [RISC-V and Xtensa Targets section of the The Rust on ESP Book](https://docs.esp-rs.org/book/installation/riscv-and-xtensa.html).

4
src/tools/tidy/src/target_policy.rs
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@ -12,6 +12,10 @@
// FIXME: disabled since it fails on CI saying the csky component is missing
"csky_unknown_linux_gnuabiv2",
"csky_unknown_linux_gnuabiv2hf",
// FIXME: disabled since it requires a custom LLVM until the upstream LLVM adds support for the target (https://github.com/espressif/llvm-project/issues/4)
"xtensa_esp32_none_elf",
"xtensa_esp32s2_none_elf",
"xtensa_esp32s3_none_elf",
];
pub fn check(root_path: &Path, bad: &mut bool) {

13
tests/assembly/targets/targets-elf.rs
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@ -573,7 +573,18 @@
//@ revisions: x86_64_wrs_vxworks
//@ [x86_64_wrs_vxworks] compile-flags: --target x86_64-wrs-vxworks
//@ [x86_64_wrs_vxworks] needs-llvm-components: x86
// FIXME: disabled since it requires a custom LLVM until the upstream LLVM adds support for the target (https://github.com/espressif/llvm-project/issues/4)
/*
revisions: xtensa_esp32_none_elf
[xtensa_esp32_none_elf] compile-flags: --target xtensa-esp32-none-elf
[xtensa_esp32_none_elf] needs-llvm-components: xtensa
revisions: xtensa_esp32s2_none_elf
[xtensa_esp32s2_none_elf] compile-flags: --target xtensa-esp32s2-none-elf
[xtensa_esp32s2_none_elf] needs-llvm-components: xtensa
revisions: xtensa_esp32s3_none_elf
[xtensa_esp32s3_none_elf] compile-flags: --target xtensa-esp32s3-none-elf
[xtensa_esp32s3_none_elf] needs-llvm-components: xtensa
*/
// Sanity-check that each target can produce assembly code.
#![feature(no_core, lang_items)]

2
tests/ui/check-cfg/well-known-values.stderr
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@ -129,7 +129,7 @@ warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`
LL | target_arch = "_UNEXPECTED_VALUE",
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
= note: expected values for `target_arch` are: `aarch64`, `arm`, `arm64ec`, `avr`, `bpf`, `csky`, `hexagon`, `loongarch64`, `m68k`, `mips`, `mips32r6`, `mips64`, `mips64r6`, `msp430`, `nvptx64`, `powerpc`, `powerpc64`, `riscv32`, `riscv64`, `s390x`, `sparc`, `sparc64`, `wasm32`, `wasm64`, `x86`, and `x86_64`
= note: expected values for `target_arch` are: `aarch64`, `arm`, `arm64ec`, `avr`, `bpf`, `csky`, `hexagon`, `loongarch64`, `m68k`, `mips`, `mips32r6`, `mips64`, `mips64r6`, `msp430`, `nvptx64`, `powerpc`, `powerpc64`, `riscv32`, `riscv64`, `s390x`, `sparc`, `sparc64`, `wasm32`, `wasm64`, `x86`, `x86_64`, and `xtensa`
= note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg.html> for more information about checking conditional configuration
warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`