Auto merge of #96942 - Dylan-DPC:rollup-p8bcly2, r=Dylan-DPC

Rollup of 4 pull requests

Successful merges:

 - #91518 (Add readable rustdoc display for RISC-V target)
 - #95281 (Fix inaccurate function name in `rustc_const_eval` docs)
 - #96898 (logging: add env var to control verbose scope entry/exit logging)
 - #96936 (⬆️ rust-analyzer)

Failed merges:

r? `@ghost`
`@rustbot` modify labels: rollup
This commit is contained in:
bors 2022-05-11 13:47:38 +00:00
commit 08b4f1be33
5 changed files with 19 additions and 4 deletions

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@ -520,8 +520,8 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> {
Ok(OpTy { op, layout: place.layout })
}
// Evaluate a place with the goal of reading from it. This lets us sometimes
// avoid allocations.
/// Evaluate a place with the goal of reading from it. This lets us sometimes
/// avoid allocations.
pub fn eval_place_to_op(
&self,
place: mir::Place<'tcx>,

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@ -625,7 +625,7 @@ where
}
/// Computes a place. You should only use this if you intend to write into this
/// place; for reading, a more efficient alternative is `eval_place_for_read`.
/// place; for reading, a more efficient alternative is `eval_place_to_op`.
#[instrument(skip(self), level = "debug")]
pub fn eval_place(
&mut self,

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@ -67,11 +67,24 @@ pub fn init_env_logger(env: &str) -> Result<(), Error> {
Err(VarError::NotUnicode(_value)) => return Err(Error::NonUnicodeColorValue),
};
let verbose_entry_exit = match env::var_os(String::from(env) + "_ENTRY_EXIT") {
None => false,
Some(v) => {
if &v == "0" {
false
} else {
true
}
}
};
let layer = tracing_tree::HierarchicalLayer::default()
.with_writer(io::stderr)
.with_indent_lines(true)
.with_ansi(color_logs)
.with_targets(true)
.with_verbose_exit(verbose_entry_exit)
.with_verbose_entry(verbose_entry_exit)
.with_indent_amount(2);
#[cfg(parallel_compiler)]
let layer = layer.with_thread_ids(true).with_thread_names(true);

View File

@ -517,6 +517,8 @@ impl<'a> fmt::Display for Display<'a> {
"msp430" => "MSP430",
"powerpc" => "PowerPC",
"powerpc64" => "PowerPC-64",
"riscv32" => "RISC-V RV32",
"riscv64" => "RISC-V RV64",
"s390x" => "s390x",
"sparc64" => "SPARC64",
"wasm32" | "wasm64" => "WebAssembly",

@ -1 +1 @@
Subproject commit 5dce1ff0212e467271c9e895478670c74d847ee9
Subproject commit 5d5bbec9b60010dd7389a084c56693baf6bda780