2023-02-24 15:33:22 -06:00
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- // MIR for `unchecked_shr_signed_smaller` before Inline
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+ // MIR for `unchecked_shr_signed_smaller` after Inline
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fn unchecked_shr_signed_smaller(_1: i16, _2: u32) -> i16 {
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debug a => _1; // in scope 0 at $DIR/unchecked_shifts.rs:+0:44: +0:45
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debug b => _2; // in scope 0 at $DIR/unchecked_shifts.rs:+0:52: +0:53
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let mut _0: i16; // return place in scope 0 at $DIR/unchecked_shifts.rs:+0:63: +0:66
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let mut _3: i16; // in scope 0 at $DIR/unchecked_shifts.rs:+1:5: +1:6
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let mut _4: u32; // in scope 0 at $DIR/unchecked_shifts.rs:+1:21: +1:22
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2023-04-05 03:44:20 -05:00
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+ scope 1 (inlined core::num::<impl i16>::unchecked_shr) { // at $DIR/unchecked_shifts.rs:17:7: 17:23
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2023-02-24 15:33:22 -06:00
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+ debug self => _3; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
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+ debug rhs => _4; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
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2023-04-17 03:22:16 -05:00
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+ let mut _5: i16; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ let mut _6: (u32,); // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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2023-04-22 18:15:39 -05:00
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+ let mut _7: u32; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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2023-02-24 15:33:22 -06:00
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+ scope 2 {
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2023-04-22 18:15:39 -05:00
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+ scope 3 (inlined core::num::<impl i16>::unchecked_shr::conv) { // at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ debug x => _7; // in scope 3 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ let mut _8: std::option::Option<i16>; // in scope 3 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ let mut _9: std::result::Result<i16, std::num::TryFromIntError>; // in scope 3 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ scope 4 {
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+ scope 5 (inlined <u32 as TryInto<i16>>::try_into) { // at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ debug self => _7; // in scope 5 at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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+ scope 6 (inlined convert::num::<impl TryFrom<u32> for i16>::try_from) { // at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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+ debug u => _7; // in scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ let mut _10: bool; // in scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ let mut _11: u32; // in scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ let mut _12: i16; // in scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ }
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+ }
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+ scope 7 (inlined Result::<i16, TryFromIntError>::ok) { // at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ debug self => _9; // in scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ let mut _13: isize; // in scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ let _14: i16; // in scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ scope 8 {
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+ debug x => _14; // in scope 8 at $SRC_DIR/core/src/result.rs:LL:COL
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+ }
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+ }
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+ scope 9 (inlined #[track_caller] Option::<i16>::unwrap_unchecked) { // at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ debug self => _8; // in scope 9 at $SRC_DIR/core/src/option.rs:LL:COL
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+ let mut _15: &std::option::Option<i16>; // in scope 9 at $SRC_DIR/core/src/option.rs:LL:COL
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+ let mut _16: isize; // in scope 9 at $SRC_DIR/core/src/option.rs:LL:COL
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+ scope 10 {
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+ debug val => _5; // in scope 10 at $SRC_DIR/core/src/option.rs:LL:COL
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+ }
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+ scope 11 {
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+ scope 13 (inlined unreachable_unchecked) { // at $SRC_DIR/core/src/option.rs:LL:COL
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+ scope 14 {
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+ scope 15 (inlined unreachable_unchecked::runtime) { // at $SRC_DIR/core/src/intrinsics.rs:LL:COL
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+ }
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+ }
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+ }
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+ }
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+ scope 12 (inlined Option::<i16>::is_some) { // at $SRC_DIR/core/src/option.rs:LL:COL
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+ debug self => _15; // in scope 12 at $SRC_DIR/core/src/option.rs:LL:COL
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+ }
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+ }
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+ }
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+ }
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2023-02-24 15:33:22 -06:00
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+ }
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+ }
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bb0: {
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StorageLive(_3); // scope 0 at $DIR/unchecked_shifts.rs:+1:5: +1:6
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_3 = _1; // scope 0 at $DIR/unchecked_shifts.rs:+1:5: +1:6
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StorageLive(_4); // scope 0 at $DIR/unchecked_shifts.rs:+1:21: +1:22
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_4 = _2; // scope 0 at $DIR/unchecked_shifts.rs:+1:21: +1:22
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- _0 = core::num::<impl i16>::unchecked_shr(move _3, move _4) -> bb1; // scope 0 at $DIR/unchecked_shifts.rs:+1:5: +1:23
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2023-04-22 18:15:39 -05:00
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- // mir::Constant
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- // + span: $DIR/unchecked_shifts.rs:17:7: 17:20
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- // + literal: Const { ty: unsafe fn(i16, u32) -> i16 {core::num::<impl i16>::unchecked_shr}, val: Value(<ZST>) }
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2023-04-17 03:22:16 -05:00
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+ StorageLive(_5); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageLive(_6); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ _6 = (_4,); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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2023-04-22 18:15:39 -05:00
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+ StorageLive(_7); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ _7 = move (_6.0: u32); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageLive(_8); // scope 4 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageLive(_9); // scope 4 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageLive(_10); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ StorageLive(_11); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ _11 = const 32767_u32; // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ _10 = Gt(_7, move _11); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ StorageDead(_11); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ switchInt(move _10) -> [0: bb3, otherwise: bb2]; // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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2023-02-24 15:33:22 -06:00
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}
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bb1: {
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2023-04-17 03:22:16 -05:00
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+ StorageDead(_5); // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
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2023-02-24 15:33:22 -06:00
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StorageDead(_4); // scope 0 at $DIR/unchecked_shifts.rs:+1:22: +1:23
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StorageDead(_3); // scope 0 at $DIR/unchecked_shifts.rs:+1:22: +1:23
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return; // scope 0 at $DIR/unchecked_shifts.rs:+2:2: +2:2
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2023-04-22 18:15:39 -05:00
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+ }
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+
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+ bb2: {
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+ _9 = Result::<i16, TryFromIntError>::Err(const TryFromIntError(())); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ // mir::Constant
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+ // + span: no-location
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+ // + literal: Const { ty: TryFromIntError, val: Value(<ZST>) }
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+ goto -> bb4; // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ }
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+
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+ bb3: {
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+ StorageLive(_12); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ _12 = _7 as i16 (IntToInt); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ _9 = Result::<i16, TryFromIntError>::Ok(move _12); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ StorageDead(_12); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ goto -> bb4; // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ }
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+
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+ bb4: {
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+ StorageDead(_10); // scope 6 at $SRC_DIR/core/src/convert/num.rs:LL:COL
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+ StorageLive(_14); // scope 4 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ _13 = discriminant(_9); // scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ switchInt(move _13) -> [0: bb7, 1: bb5, otherwise: bb6]; // scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ }
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+
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+ bb5: {
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+ _8 = Option::<i16>::None; // scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ goto -> bb8; // scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ }
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+
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+ bb6: {
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+ unreachable; // scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ }
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+
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+ bb7: {
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+ _14 = move ((_9 as Ok).0: i16); // scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ _8 = Option::<i16>::Some(move _14); // scope 8 at $SRC_DIR/core/src/result.rs:LL:COL
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+ goto -> bb8; // scope 7 at $SRC_DIR/core/src/result.rs:LL:COL
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+ }
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+
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+ bb8: {
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+ StorageDead(_14); // scope 4 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageDead(_9); // scope 4 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageLive(_15); // scope 4 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ _16 = discriminant(_8); // scope 9 at $SRC_DIR/core/src/option.rs:LL:COL
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+ switchInt(move _16) -> [1: bb9, otherwise: bb6]; // scope 9 at $SRC_DIR/core/src/option.rs:LL:COL
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+ }
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+
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+ bb9: {
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+ _5 = move ((_8 as Some).0: i16); // scope 9 at $SRC_DIR/core/src/option.rs:LL:COL
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+ StorageDead(_15); // scope 4 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageDead(_8); // scope 4 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageDead(_7); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ StorageDead(_6); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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+ _0 = unchecked_shr::<i16>(_3, move _5) -> [return: bb1, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
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+ // mir::Constant
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+ // + span: $SRC_DIR/core/src/num/int_macros.rs:LL:COL
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+ // + literal: Const { ty: unsafe extern "rust-intrinsic" fn(i16, i16) -> i16 {unchecked_shr::<i16>}, val: Value(<ZST>) }
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2023-02-24 15:33:22 -06:00
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}
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}
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