2018-10-03 18:21:52 +02:00
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use crate::prelude::*;
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2019-02-28 10:55:21 +01:00
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use rustc::ty::subst::SubstsRef;
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2019-07-29 12:43:24 +02:00
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macro intrinsic_pat {
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2018-10-05 19:55:06 +02:00
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(_) => {
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_
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2019-07-29 12:43:24 +02:00
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},
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2018-10-05 19:55:06 +02:00
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($name:ident) => {
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stringify!($name)
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2019-07-29 12:43:24 +02:00
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},
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($name:literal) => {
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stringify!($name)
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},
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($x:ident . $($xs:tt).*) => {
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concat!(stringify!($x), ".", intrinsic_pat!($($xs).*))
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2018-10-05 19:55:06 +02:00
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}
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}
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2019-07-29 12:43:24 +02:00
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macro intrinsic_arg {
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2019-07-28 11:24:33 +02:00
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(o $fx:expr, $arg:ident) => {
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2018-10-05 19:55:06 +02:00
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$arg
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2019-07-29 12:43:24 +02:00
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},
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2019-07-28 11:24:33 +02:00
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(c $fx:expr, $arg:ident) => {
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trans_operand($fx, $arg)
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2019-07-29 12:43:24 +02:00
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},
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2018-10-05 19:55:06 +02:00
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(v $fx:expr, $arg:ident) => {
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2019-07-28 11:24:33 +02:00
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trans_operand($fx, $arg).load_scalar($fx)
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2019-07-29 12:43:24 +02:00
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}
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2018-10-05 19:55:06 +02:00
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}
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2019-07-29 12:43:24 +02:00
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macro intrinsic_substs {
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($substs:expr, $index:expr,) => {},
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2018-10-05 20:11:47 +02:00
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($substs:expr, $index:expr, $first:ident $(,$rest:ident)*) => {
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let $first = $substs.type_at($index);
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intrinsic_substs!($substs, $index+1, $($rest),*);
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2019-07-29 12:43:24 +02:00
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}
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2018-10-05 20:11:47 +02:00
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}
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2019-07-29 12:43:24 +02:00
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pub macro intrinsic_match {
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($fx:expr, $intrinsic:expr, $substs:expr, $args:expr,
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_ => $unknown:block;
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$(
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$($($name:tt).*)|+ $(if $cond:expr)?, $(<$($subst:ident),*>)? ($($a:ident $arg:ident),*) $content:block;
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2018-10-05 19:55:06 +02:00
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)*) => {
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match $intrinsic {
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$(
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2019-07-29 12:43:24 +02:00
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$(intrinsic_pat!($($name).*))|* $(if $cond)? => {
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2018-10-05 20:11:47 +02:00
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#[allow(unused_parens, non_snake_case)]
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{
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$(
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intrinsic_substs!($substs, 0, $($subst),*);
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)?
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2019-07-28 11:24:33 +02:00
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if let [$($arg),*] = $args {
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let ($($arg,)*) = (
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$(intrinsic_arg!($a $fx, $arg),)*
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2018-10-05 19:55:06 +02:00
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);
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2018-10-05 20:11:47 +02:00
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#[warn(unused_parens, non_snake_case)]
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{
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$content
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}
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} else {
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bug!("wrong number of args for intrinsic {:?}", $intrinsic);
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2018-10-05 19:55:06 +02:00
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}
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}
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}
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)*
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2019-07-29 12:43:24 +02:00
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_ => $unknown,
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2018-10-05 19:55:06 +02:00
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}
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2019-07-29 12:43:24 +02:00
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}
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2018-10-05 19:55:06 +02:00
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}
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2019-07-27 16:51:48 +02:00
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macro_rules! call_intrinsic_match {
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($fx:expr, $intrinsic:expr, $substs:expr, $ret:expr, $destination:expr, $args:expr, $(
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$name:ident($($arg:ident),*) -> $ty:ident => $func:ident,
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)*) => {
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match $intrinsic {
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$(
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stringify!($name) => {
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assert!($substs.is_noop());
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2019-07-28 11:24:33 +02:00
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if let [$(ref $arg),*] = *$args {
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let ($($arg,)*) = (
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$(trans_operand($fx, $arg),)*
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);
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2019-07-27 16:51:48 +02:00
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let res = $fx.easy_call(stringify!($func), &[$($arg),*], $fx.tcx.types.$ty);
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$ret.write_cvalue($fx, res);
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if let Some((_, dest)) = $destination {
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let ret_ebb = $fx.get_ebb(dest);
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$fx.bcx.ins().jump(ret_ebb, &[]);
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return;
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} else {
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unreachable!();
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}
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} else {
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bug!("wrong number of args for intrinsic {:?}", $intrinsic);
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}
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}
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)*
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_ => {}
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}
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}
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}
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2018-10-06 10:24:09 +02:00
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macro_rules! atomic_binop_return_old {
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($fx:expr, $op:ident<$T:ident>($ptr:ident, $src:ident) -> $ret:ident) => {
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2018-11-12 07:23:39 -08:00
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let clif_ty = $fx.clif_type($T).unwrap();
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2018-10-06 10:24:09 +02:00
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let old = $fx.bcx.ins().load(clif_ty, MemFlags::new(), $ptr, 0);
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2019-03-06 20:34:57 +01:00
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let new = $fx.bcx.ins().$op(old, $src);
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2018-10-06 10:24:09 +02:00
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$fx.bcx.ins().store(MemFlags::new(), new, $ptr, 0);
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2019-06-11 16:25:07 +02:00
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$ret.write_cvalue($fx, CValue::by_val(old, $fx.layout_of($T)));
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2018-10-06 10:24:09 +02:00
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};
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}
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macro_rules! atomic_minmax {
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($fx:expr, $cc:expr, <$T:ident> ($ptr:ident, $src:ident) -> $ret:ident) => {
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// Read old
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2018-11-12 07:23:39 -08:00
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let clif_ty = $fx.clif_type($T).unwrap();
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2018-10-06 10:24:09 +02:00
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let old = $fx.bcx.ins().load(clif_ty, MemFlags::new(), $ptr, 0);
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// Compare
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let is_eq = $fx.bcx.ins().icmp(IntCC::SignedGreaterThan, old, $src);
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2018-10-07 11:18:08 +02:00
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let new = crate::common::codegen_select(&mut $fx.bcx, is_eq, old, $src);
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2018-10-06 10:24:09 +02:00
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// Write new
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$fx.bcx.ins().store(MemFlags::new(), new, $ptr, 0);
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2019-06-11 16:25:07 +02:00
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let ret_val = CValue::by_val(old, $ret.layout());
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2018-10-06 10:24:09 +02:00
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$ret.write_cvalue($fx, ret_val);
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};
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}
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2019-07-29 12:43:24 +02:00
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pub fn lane_type_and_count<'tcx>(
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2019-07-27 17:48:24 +02:00
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fx: &FunctionCx<'_, 'tcx, impl Backend>,
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layout: TyLayout<'tcx>,
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intrinsic: &str,
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2019-07-28 11:24:33 +02:00
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) -> (TyLayout<'tcx>, u32) {
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2019-07-28 10:24:57 +02:00
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assert!(layout.ty.is_simd());
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2019-07-27 17:48:24 +02:00
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let lane_count = match layout.fields {
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2019-07-28 11:24:33 +02:00
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layout::FieldPlacement::Array { stride: _, count } => u32::try_from(count).unwrap(),
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2019-07-27 17:48:24 +02:00
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_ => panic!("Non vector type {:?} passed to or returned from simd_* intrinsic {}", layout.ty, intrinsic),
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};
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let lane_layout = layout.field(fx, 0);
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(lane_layout, lane_count)
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}
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2019-07-30 14:37:20 +02:00
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pub fn simd_for_each_lane<'tcx, B: Backend>(
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2019-07-27 17:48:24 +02:00
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fx: &mut FunctionCx<'_, 'tcx, B>,
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intrinsic: &str,
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x: CValue<'tcx>,
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y: CValue<'tcx>,
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ret: CPlace<'tcx>,
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f: impl Fn(&mut FunctionCx<'_, 'tcx, B>, TyLayout<'tcx>, TyLayout<'tcx>, Value, Value) -> CValue<'tcx>,
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) {
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assert_eq!(x.layout(), y.layout());
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let layout = x.layout();
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let (lane_layout, lane_count) = lane_type_and_count(fx, layout, intrinsic);
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let (ret_lane_layout, ret_lane_count) = lane_type_and_count(fx, ret.layout(), intrinsic);
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assert_eq!(lane_count, ret_lane_count);
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for lane in 0..lane_count {
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2019-07-28 11:24:33 +02:00
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let lane = mir::Field::new(lane.try_into().unwrap());
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2019-07-27 17:48:24 +02:00
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let x_lane = x.value_field(fx, lane).load_scalar(fx);
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let y_lane = y.value_field(fx, lane).load_scalar(fx);
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let res_lane = f(fx, lane_layout, ret_lane_layout, x_lane, y_lane);
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ret.place_field(fx, lane).write_cvalue(fx, res_lane);
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}
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}
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2019-07-30 14:37:20 +02:00
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pub fn bool_to_zero_or_max_uint<'tcx>(
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2019-07-28 09:45:01 +02:00
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fx: &mut FunctionCx<'_, 'tcx, impl Backend>,
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layout: TyLayout<'tcx>,
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val: Value,
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) -> CValue<'tcx> {
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let ty = fx.clif_type(layout.ty).unwrap();
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2019-07-30 14:37:20 +02:00
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let int_ty = match ty {
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types::F32 => types::I32,
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types::F64 => types::I64,
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ty => ty,
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};
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let zero = fx.bcx.ins().iconst(int_ty, 0);
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let max = fx.bcx.ins().iconst(int_ty, (u64::max_value() >> (64 - int_ty.bits())) as i64);
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let mut res = crate::common::codegen_select(&mut fx.bcx, val, max, zero);
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if ty.is_float() {
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res = fx.bcx.ins().bitcast(ty, res);
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}
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2019-07-28 09:45:01 +02:00
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CValue::by_val(res, layout)
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}
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macro_rules! simd_cmp {
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($fx:expr, $intrinsic:expr, $cc:ident($x:ident, $y:ident) -> $ret:ident) => {
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2019-07-30 14:37:20 +02:00
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simd_for_each_lane($fx, $intrinsic, $x, $y, $ret, |fx, lane_layout, res_lane_layout, x_lane, y_lane| {
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let res_lane = match lane_layout.ty.sty {
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ty::Uint(_) | ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc, x_lane, y_lane),
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_ => unreachable!("{:?}", lane_layout.ty),
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};
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2019-07-28 09:45:01 +02:00
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bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
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2019-07-27 17:52:57 +02:00
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});
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};
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2019-07-28 09:45:01 +02:00
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($fx:expr, $intrinsic:expr, $cc_u:ident|$cc_s:ident($x:ident, $y:ident) -> $ret:ident) => {
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simd_for_each_lane($fx, $intrinsic, $x, $y, $ret, |fx, lane_layout, res_lane_layout, x_lane, y_lane| {
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2019-07-27 17:52:57 +02:00
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let res_lane = match lane_layout.ty.sty {
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ty::Uint(_) => fx.bcx.ins().icmp(IntCC::$cc_u, x_lane, y_lane),
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ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc_s, x_lane, y_lane),
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_ => unreachable!("{:?}", lane_layout.ty),
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};
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2019-07-28 09:45:01 +02:00
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bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
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2019-07-27 17:52:57 +02:00
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});
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};
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2019-07-28 09:45:01 +02:00
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}
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2019-07-30 14:37:20 +02:00
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macro_rules! simd_int_binop {
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2019-07-27 17:48:24 +02:00
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($fx:expr, $intrinsic:expr, $op:ident($x:ident, $y:ident) -> $ret:ident) => {
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2019-07-30 14:37:20 +02:00
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simd_for_each_lane($fx, $intrinsic, $x, $y, $ret, |fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
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let res_lane = match lane_layout.ty.sty {
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ty::Uint(_) | ty::Int(_) => fx.bcx.ins().$op(x_lane, y_lane),
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_ => unreachable!("{:?}", lane_layout.ty),
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};
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2019-07-27 17:48:24 +02:00
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CValue::by_val(res_lane, ret_lane_layout)
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});
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};
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($fx:expr, $intrinsic:expr, $op_u:ident|$op_s:ident($x:ident, $y:ident) -> $ret:ident) => {
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simd_for_each_lane($fx, $intrinsic, $x, $y, $ret, |fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
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let res_lane = match lane_layout.ty.sty {
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ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
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ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
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_ => unreachable!("{:?}", lane_layout.ty),
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};
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CValue::by_val(res_lane, ret_lane_layout)
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});
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};
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}
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2019-07-30 14:37:20 +02:00
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macro_rules! simd_int_flt_binop {
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($fx:expr, $intrinsic:expr, $op:ident|$op_f:ident($x:ident, $y:ident) -> $ret:ident) => {
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simd_for_each_lane($fx, $intrinsic, $x, $y, $ret, |fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
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let res_lane = match lane_layout.ty.sty {
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ty::Uint(_) | ty::Int(_) => fx.bcx.ins().$op(x_lane, y_lane),
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ty::Float(_) => fx.bcx.ins().$op_f(x_lane, y_lane),
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_ => unreachable!("{:?}", lane_layout.ty),
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};
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CValue::by_val(res_lane, ret_lane_layout)
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});
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};
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($fx:expr, $intrinsic:expr, $op_u:ident|$op_s:ident|$op_f:ident($x:ident, $y:ident) -> $ret:ident) => {
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simd_for_each_lane($fx, $intrinsic, $x, $y, $ret, |fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
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let res_lane = match lane_layout.ty.sty {
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ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
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ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
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ty::Float(_) => fx.bcx.ins().$op_f(x_lane, y_lane),
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_ => unreachable!("{:?}", lane_layout.ty),
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};
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CValue::by_val(res_lane, ret_lane_layout)
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});
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};
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}
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macro_rules! simd_flt_binop {
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($fx:expr, $intrinsic:expr, $op:ident($x:ident, $y:ident) -> $ret:ident) => {
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simd_for_each_lane($fx, $intrinsic, $x, $y, $ret, |fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
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let res_lane = match lane_layout.ty.sty {
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ty::Float(_) => fx.bcx.ins().$op(x_lane, y_lane),
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_ => unreachable!("{:?}", lane_layout.ty),
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};
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|
|
CValue::by_val(res_lane, ret_lane_layout)
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-10-03 18:21:52 +02:00
|
|
|
pub fn codegen_intrinsic_call<'a, 'tcx: 'a>(
|
|
|
|
fx: &mut FunctionCx<'a, 'tcx, impl Backend>,
|
|
|
|
def_id: DefId,
|
2019-02-28 10:55:21 +01:00
|
|
|
substs: SubstsRef<'tcx>,
|
2019-07-28 11:24:33 +02:00
|
|
|
args: &[mir::Operand<'tcx>],
|
2018-10-03 18:21:52 +02:00
|
|
|
destination: Option<(CPlace<'tcx>, BasicBlock)>,
|
|
|
|
) {
|
|
|
|
let intrinsic = fx.tcx.item_name(def_id).as_str();
|
|
|
|
let intrinsic = &intrinsic[..];
|
|
|
|
|
|
|
|
let ret = match destination {
|
|
|
|
Some((place, _)) => place,
|
|
|
|
None => {
|
|
|
|
// Insert non returning intrinsics here
|
|
|
|
match intrinsic {
|
|
|
|
"abort" => {
|
2019-06-17 21:19:08 +02:00
|
|
|
trap_panic(fx, "Called intrinsic::abort.");
|
2018-10-03 18:21:52 +02:00
|
|
|
}
|
|
|
|
"unreachable" => {
|
2019-03-23 13:06:35 +01:00
|
|
|
trap_unreachable(fx, "[corruption] Called intrinsic::unreachable.");
|
2018-10-03 18:21:52 +02:00
|
|
|
}
|
|
|
|
_ => unimplemented!("unsupported instrinsic {}", intrinsic),
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
let u64_layout = fx.layout_of(fx.tcx.types.u64);
|
|
|
|
let usize_layout = fx.layout_of(fx.tcx.types.usize);
|
|
|
|
|
2019-07-27 16:51:48 +02:00
|
|
|
call_intrinsic_match! {
|
|
|
|
fx, intrinsic, substs, ret, destination, args,
|
|
|
|
expf32(flt) -> f32 => expf,
|
|
|
|
expf64(flt) -> f64 => exp,
|
|
|
|
exp2f32(flt) -> f32 => exp2f,
|
|
|
|
exp2f64(flt) -> f64 => exp2,
|
|
|
|
sqrtf32(flt) -> f32 => sqrtf,
|
|
|
|
sqrtf64(flt) -> f64 => sqrt,
|
|
|
|
powif32(a, x) -> f32 => __powisf2, // compiler-builtins
|
|
|
|
powif64(a, x) -> f64 => __powidf2, // compiler-builtins
|
|
|
|
logf32(flt) -> f32 => logf,
|
|
|
|
logf64(flt) -> f64 => log,
|
2019-08-12 15:54:24 +02:00
|
|
|
log2f32(flt) -> f32 => log2f,
|
|
|
|
log2f64(flt) -> f64 => log2,
|
2019-07-27 16:51:48 +02:00
|
|
|
fabsf32(flt) -> f32 => fabsf,
|
|
|
|
fabsf64(flt) -> f64 => fabs,
|
|
|
|
fmaf32(x, y, z) -> f32 => fmaf,
|
|
|
|
fmaf64(x, y, z) -> f64 => fma,
|
|
|
|
|
|
|
|
// rounding variants
|
|
|
|
floorf32(flt) -> f32 => floorf,
|
|
|
|
floorf64(flt) -> f64 => floor,
|
|
|
|
ceilf32(flt) -> f32 => ceilf,
|
|
|
|
ceilf64(flt) -> f64 => ceil,
|
|
|
|
truncf32(flt) -> f32 => truncf,
|
|
|
|
truncf64(flt) -> f64 => trunc,
|
|
|
|
roundf32(flt) -> f32 => roundf,
|
|
|
|
roundf64(flt) -> f64 => round,
|
|
|
|
|
|
|
|
// trigonometry
|
|
|
|
sinf32(flt) -> f32 => sinf,
|
|
|
|
sinf64(flt) -> f64 => sin,
|
|
|
|
cosf32(flt) -> f32 => cosf,
|
|
|
|
cosf64(flt) -> f64 => cos,
|
|
|
|
tanf32(flt) -> f32 => tanf,
|
|
|
|
tanf64(flt) -> f64 => tan,
|
|
|
|
}
|
|
|
|
|
2018-10-05 19:55:06 +02:00
|
|
|
intrinsic_match! {
|
2018-10-05 20:11:47 +02:00
|
|
|
fx, intrinsic, substs, args,
|
2019-07-29 12:43:24 +02:00
|
|
|
_ => {
|
|
|
|
unimpl!("unsupported intrinsic {}", intrinsic)
|
|
|
|
};
|
2018-10-05 19:55:06 +02:00
|
|
|
|
2018-10-05 20:11:47 +02:00
|
|
|
assume, (c _a) {};
|
|
|
|
likely | unlikely, (c a) {
|
2018-10-05 19:55:06 +02:00
|
|
|
ret.write_cvalue(fx, a);
|
|
|
|
};
|
2019-02-11 18:49:59 +01:00
|
|
|
breakpoint, () {
|
|
|
|
fx.bcx.ins().debugtrap();
|
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
copy | copy_nonoverlapping, <elem_ty> (v src, v dst, v count) {
|
2018-10-03 18:21:52 +02:00
|
|
|
let elem_size: u64 = fx.layout_of(elem_ty).size.bytes();
|
|
|
|
let elem_size = fx
|
|
|
|
.bcx
|
|
|
|
.ins()
|
2018-11-03 13:14:28 +01:00
|
|
|
.iconst(fx.pointer_type, elem_size as i64);
|
2018-10-03 18:21:52 +02:00
|
|
|
assert_eq!(args.len(), 3);
|
|
|
|
let byte_amount = fx.bcx.ins().imul(count, elem_size);
|
|
|
|
|
|
|
|
if intrinsic.ends_with("_nonoverlapping") {
|
2018-11-09 18:03:47 +01:00
|
|
|
fx.bcx.call_memcpy(fx.module.target_config(), dst, src, byte_amount);
|
2018-10-03 18:21:52 +02:00
|
|
|
} else {
|
2018-11-09 18:03:47 +01:00
|
|
|
fx.bcx.call_memmove(fx.module.target_config(), dst, src, byte_amount);
|
2018-10-03 18:21:52 +02:00
|
|
|
}
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
discriminant_value, (c val) {
|
2019-02-16 17:18:38 +01:00
|
|
|
let pointee_layout = fx.layout_of(val.layout().ty.builtin_deref(true).unwrap().ty);
|
2019-06-11 16:30:47 +02:00
|
|
|
let place = CPlace::for_addr(val.load_scalar(fx), pointee_layout);
|
2019-02-16 17:18:38 +01:00
|
|
|
let discr = crate::base::trans_get_discriminant(fx, place, ret.layout());
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, discr);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
size_of, <T> () {
|
|
|
|
let size_of = fx.layout_of(T).size.bytes();
|
2019-07-24 17:16:31 +02:00
|
|
|
let size_of = CValue::const_val(fx, usize_layout.ty, size_of.into());
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, size_of);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
size_of_val, <T> (c ptr) {
|
|
|
|
let layout = fx.layout_of(T);
|
2018-12-29 15:33:34 +01:00
|
|
|
let size = if layout.is_unsized() {
|
2019-03-02 21:09:28 +01:00
|
|
|
let (_ptr, info) = ptr.load_scalar_pair(fx);
|
2018-12-29 15:33:34 +01:00
|
|
|
let (size, _align) = crate::unsize::size_and_align_of_dst(fx, layout.ty, info);
|
|
|
|
size
|
|
|
|
} else {
|
|
|
|
fx
|
2018-10-03 18:21:52 +02:00
|
|
|
.bcx
|
|
|
|
.ins()
|
2018-12-29 15:33:34 +01:00
|
|
|
.iconst(fx.pointer_type, layout.size.bytes() as i64)
|
2018-10-03 18:21:52 +02:00
|
|
|
};
|
2019-06-11 16:25:07 +02:00
|
|
|
ret.write_cvalue(fx, CValue::by_val(size, usize_layout));
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
min_align_of, <T> () {
|
2018-11-24 11:23:49 +01:00
|
|
|
let min_align = fx.layout_of(T).align.abi.bytes();
|
2019-07-24 17:16:31 +02:00
|
|
|
let min_align = CValue::const_val(fx, usize_layout.ty, min_align.into());
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, min_align);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
min_align_of_val, <T> (c ptr) {
|
|
|
|
let layout = fx.layout_of(T);
|
2018-12-29 15:33:34 +01:00
|
|
|
let align = if layout.is_unsized() {
|
2019-03-02 21:09:28 +01:00
|
|
|
let (_ptr, info) = ptr.load_scalar_pair(fx);
|
2018-12-29 15:33:34 +01:00
|
|
|
let (_size, align) = crate::unsize::size_and_align_of_dst(fx, layout.ty, info);
|
|
|
|
align
|
|
|
|
} else {
|
|
|
|
fx
|
2018-10-03 18:21:52 +02:00
|
|
|
.bcx
|
|
|
|
.ins()
|
2018-12-29 15:33:34 +01:00
|
|
|
.iconst(fx.pointer_type, layout.align.abi.bytes() as i64)
|
2018-10-03 18:21:52 +02:00
|
|
|
};
|
2019-06-11 16:25:07 +02:00
|
|
|
ret.write_cvalue(fx, CValue::by_val(align, usize_layout));
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2019-06-23 16:33:34 +02:00
|
|
|
pref_align_of, <T> () {
|
|
|
|
let pref_align = fx.layout_of(T).align.pref.bytes();
|
2019-07-24 17:16:31 +02:00
|
|
|
let pref_align = CValue::const_val(fx, usize_layout.ty, pref_align.into());
|
2019-06-23 16:33:34 +02:00
|
|
|
ret.write_cvalue(fx, pref_align);
|
|
|
|
};
|
|
|
|
|
|
|
|
|
2018-10-05 20:11:47 +02:00
|
|
|
type_id, <T> () {
|
|
|
|
let type_id = fx.tcx.type_id_hash(T);
|
2019-07-24 17:16:31 +02:00
|
|
|
let type_id = CValue::const_val(fx, u64_layout.ty, type_id.into());
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, type_id);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2019-06-23 16:33:34 +02:00
|
|
|
type_name, <T> () {
|
|
|
|
let type_name = fx.tcx.type_name(T);
|
2019-07-13 11:07:07 +02:00
|
|
|
let type_name = crate::constant::trans_const_value(fx, type_name);
|
2019-06-23 16:33:34 +02:00
|
|
|
ret.write_cvalue(fx, type_name);
|
|
|
|
};
|
|
|
|
|
2018-11-13 18:50:45 +01:00
|
|
|
_ if intrinsic.starts_with("unchecked_") || intrinsic == "exact_div", (c x, c y) {
|
2019-03-04 18:57:09 +01:00
|
|
|
// FIXME trap on overflow
|
2018-10-03 18:21:52 +02:00
|
|
|
let bin_op = match intrinsic {
|
2019-06-23 10:47:16 +02:00
|
|
|
"unchecked_sub" => BinOp::Sub,
|
2018-11-13 18:50:45 +01:00
|
|
|
"unchecked_div" | "exact_div" => BinOp::Div,
|
2018-10-03 18:21:52 +02:00
|
|
|
"unchecked_rem" => BinOp::Rem,
|
|
|
|
"unchecked_shl" => BinOp::Shl,
|
|
|
|
"unchecked_shr" => BinOp::Shr,
|
|
|
|
_ => unimplemented!("intrinsic {}", intrinsic),
|
|
|
|
};
|
|
|
|
let res = match ret.layout().ty.sty {
|
|
|
|
ty::Uint(_) => crate::base::trans_int_binop(
|
|
|
|
fx,
|
|
|
|
bin_op,
|
2018-10-05 19:55:06 +02:00
|
|
|
x,
|
|
|
|
y,
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.layout().ty,
|
|
|
|
false,
|
|
|
|
),
|
|
|
|
ty::Int(_) => crate::base::trans_int_binop(
|
|
|
|
fx,
|
|
|
|
bin_op,
|
2018-10-05 19:55:06 +02:00
|
|
|
x,
|
|
|
|
y,
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.layout().ty,
|
|
|
|
true,
|
|
|
|
),
|
|
|
|
_ => panic!(),
|
|
|
|
};
|
|
|
|
ret.write_cvalue(fx, res);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
_ if intrinsic.ends_with("_with_overflow"), <T> (c x, c y) {
|
2018-10-05 19:55:06 +02:00
|
|
|
assert_eq!(x.layout().ty, y.layout().ty);
|
2018-10-03 18:21:52 +02:00
|
|
|
let bin_op = match intrinsic {
|
|
|
|
"add_with_overflow" => BinOp::Add,
|
|
|
|
"sub_with_overflow" => BinOp::Sub,
|
|
|
|
"mul_with_overflow" => BinOp::Mul,
|
|
|
|
_ => unimplemented!("intrinsic {}", intrinsic),
|
|
|
|
};
|
2019-08-08 15:54:13 +02:00
|
|
|
|
|
|
|
let res = crate::base::trans_checked_int_binop(
|
|
|
|
fx,
|
|
|
|
bin_op,
|
|
|
|
x,
|
|
|
|
y,
|
|
|
|
ret.layout().ty,
|
2019-08-12 17:25:16 +02:00
|
|
|
type_sign(T),
|
2019-08-08 15:54:13 +02:00
|
|
|
);
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, res);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
_ if intrinsic.starts_with("overflowing_"), <T> (c x, c y) {
|
2018-10-05 19:55:06 +02:00
|
|
|
assert_eq!(x.layout().ty, y.layout().ty);
|
2018-10-03 18:21:52 +02:00
|
|
|
let bin_op = match intrinsic {
|
|
|
|
"overflowing_add" => BinOp::Add,
|
|
|
|
"overflowing_sub" => BinOp::Sub,
|
|
|
|
"overflowing_mul" => BinOp::Mul,
|
|
|
|
_ => unimplemented!("intrinsic {}", intrinsic),
|
|
|
|
};
|
2019-08-12 17:25:16 +02:00
|
|
|
let res = crate::base::trans_int_binop(
|
|
|
|
fx,
|
|
|
|
bin_op,
|
|
|
|
x,
|
|
|
|
y,
|
|
|
|
ret.layout().ty,
|
|
|
|
type_sign(T),
|
|
|
|
);
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, res);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2019-03-04 18:57:09 +01:00
|
|
|
_ if intrinsic.starts_with("saturating_"), <T> (c x, c y) {
|
|
|
|
assert_eq!(x.layout().ty, y.layout().ty);
|
|
|
|
let bin_op = match intrinsic {
|
|
|
|
"saturating_add" => BinOp::Add,
|
|
|
|
"saturating_sub" => BinOp::Sub,
|
|
|
|
_ => unimplemented!("intrinsic {}", intrinsic),
|
|
|
|
};
|
2019-08-08 15:54:13 +02:00
|
|
|
|
2019-08-12 17:25:16 +02:00
|
|
|
let signed = type_sign(T);
|
2019-08-08 15:54:13 +02:00
|
|
|
|
|
|
|
let checked_res = crate::base::trans_checked_int_binop(
|
|
|
|
fx,
|
|
|
|
bin_op,
|
|
|
|
x,
|
|
|
|
y,
|
|
|
|
fx.tcx.mk_tup([T, fx.tcx.types.bool].into_iter()),
|
|
|
|
signed,
|
|
|
|
);
|
|
|
|
|
|
|
|
let (val, has_overflow) = checked_res.load_scalar_pair(fx);
|
|
|
|
let clif_ty = fx.clif_type(T).unwrap();
|
|
|
|
|
|
|
|
// `select.i8` is not implemented by Cranelift.
|
|
|
|
let has_overflow = fx.bcx.ins().uextend(types::I32, has_overflow);
|
|
|
|
|
2019-08-12 17:25:16 +02:00
|
|
|
let (min, max) = type_min_max_value(clif_ty, signed);
|
2019-08-08 15:54:13 +02:00
|
|
|
let min = fx.bcx.ins().iconst(clif_ty, min);
|
|
|
|
let max = fx.bcx.ins().iconst(clif_ty, max);
|
|
|
|
|
|
|
|
let val = match (intrinsic, signed) {
|
|
|
|
("saturating_add", false) => fx.bcx.ins().select(has_overflow, max, val),
|
|
|
|
("saturating_sub", false) => fx.bcx.ins().select(has_overflow, min, val),
|
|
|
|
("saturating_add", true) => unimplemented!(),
|
|
|
|
("saturating_sub", true) => unimplemented!(),
|
|
|
|
_ => unreachable!(),
|
2019-03-04 18:57:09 +01:00
|
|
|
};
|
2019-08-08 15:54:13 +02:00
|
|
|
|
|
|
|
let res = CValue::by_val(val, fx.layout_of(T));
|
|
|
|
|
2019-03-04 18:57:09 +01:00
|
|
|
ret.write_cvalue(fx, res);
|
|
|
|
};
|
2018-11-16 19:50:02 +01:00
|
|
|
rotate_left, <T>(v x, v y) {
|
|
|
|
let layout = fx.layout_of(T);
|
|
|
|
let res = fx.bcx.ins().rotl(x, y);
|
2019-06-11 16:25:07 +02:00
|
|
|
ret.write_cvalue(fx, CValue::by_val(res, layout));
|
2018-11-16 19:50:02 +01:00
|
|
|
};
|
|
|
|
rotate_right, <T>(v x, v y) {
|
|
|
|
let layout = fx.layout_of(T);
|
|
|
|
let res = fx.bcx.ins().rotr(x, y);
|
2019-06-11 16:25:07 +02:00
|
|
|
ret.write_cvalue(fx, CValue::by_val(res, layout));
|
2018-11-16 19:50:02 +01:00
|
|
|
};
|
2019-02-16 13:49:42 +01:00
|
|
|
|
|
|
|
// The only difference between offset and arith_offset is regarding UB. Because Cranelift
|
|
|
|
// doesn't have UB both are codegen'ed the same way
|
|
|
|
offset | arith_offset, (c base, v offset) {
|
2019-02-11 18:49:59 +01:00
|
|
|
let pointee_ty = base.layout().ty.builtin_deref(true).unwrap().ty;
|
|
|
|
let pointee_size = fx.layout_of(pointee_ty).size.bytes();
|
|
|
|
let ptr_diff = fx.bcx.ins().imul_imm(offset, pointee_size as i64);
|
|
|
|
let base_val = base.load_scalar(fx);
|
|
|
|
let res = fx.bcx.ins().iadd(base_val, ptr_diff);
|
2019-07-28 11:24:33 +02:00
|
|
|
ret.write_cvalue(fx, CValue::by_val(res, base.layout()));
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2019-02-16 13:49:42 +01:00
|
|
|
|
2018-10-05 20:11:47 +02:00
|
|
|
transmute, <src_ty, dst_ty> (c from) {
|
2018-10-05 19:55:06 +02:00
|
|
|
assert_eq!(from.layout().ty, src_ty);
|
|
|
|
let addr = from.force_stack(fx);
|
2018-10-03 18:21:52 +02:00
|
|
|
let dst_layout = fx.layout_of(dst_ty);
|
2019-06-11 15:32:30 +02:00
|
|
|
ret.write_cvalue(fx, CValue::by_ref(addr, dst_layout))
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2019-02-24 16:46:11 +01:00
|
|
|
init, () {
|
|
|
|
if ret.layout().abi == Abi::Uninhabited {
|
2019-03-23 13:06:35 +01:00
|
|
|
crate::trap::trap_panic(fx, "[panic] Called intrinsic::init for uninhabited type.");
|
2019-02-24 16:46:11 +01:00
|
|
|
return;
|
|
|
|
}
|
2018-10-03 18:21:52 +02:00
|
|
|
|
2019-02-24 16:46:11 +01:00
|
|
|
match ret {
|
|
|
|
CPlace::NoPlace(_layout) => {}
|
|
|
|
CPlace::Var(var, layout) => {
|
|
|
|
let clif_ty = fx.clif_type(layout.ty).unwrap();
|
|
|
|
let val = match clif_ty {
|
|
|
|
types::I8 | types::I16 | types::I32 | types::I64 => fx.bcx.ins().iconst(clif_ty, 0),
|
|
|
|
types::F32 => {
|
|
|
|
let zero = fx.bcx.ins().iconst(types::I32, 0);
|
|
|
|
fx.bcx.ins().bitcast(types::F32, zero)
|
|
|
|
}
|
|
|
|
types::F64 => {
|
|
|
|
let zero = fx.bcx.ins().iconst(types::I64, 0);
|
|
|
|
fx.bcx.ins().bitcast(types::F64, zero)
|
|
|
|
}
|
|
|
|
_ => panic!("clif_type returned {}", clif_ty),
|
|
|
|
};
|
|
|
|
fx.bcx.def_var(mir_var(var), val);
|
|
|
|
}
|
|
|
|
_ => {
|
|
|
|
let addr = ret.to_addr(fx);
|
|
|
|
let layout = ret.layout();
|
|
|
|
fx.bcx.emit_small_memset(fx.module.target_config(), addr, 0, layout.size.bytes(), 1);
|
|
|
|
}
|
|
|
|
}
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2019-08-13 12:18:35 +02:00
|
|
|
uninit, () {
|
|
|
|
if ret.layout().abi == Abi::Uninhabited {
|
|
|
|
crate::trap::trap_panic(fx, "[panic] Called intrinsic::uninit for uninhabited type.");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
match ret {
|
|
|
|
CPlace::NoPlace(_layout) => unreachable!("{:?}", ret),
|
|
|
|
CPlace::Var(var, layout) => {
|
|
|
|
let clif_ty = fx.clif_type(layout.ty).unwrap();
|
|
|
|
let val = match clif_ty {
|
|
|
|
types::I8 | types::I16 | types::I32 | types::I64 => fx.bcx.ins().iconst(clif_ty, 42),
|
|
|
|
types::F32 => {
|
|
|
|
let zero = fx.bcx.ins().iconst(types::I32, 0xdeadbeef);
|
|
|
|
fx.bcx.ins().bitcast(types::F32, zero)
|
|
|
|
}
|
|
|
|
types::F64 => {
|
|
|
|
let zero = fx.bcx.ins().iconst(types::I64, 0xcafebabedeadbeefu64 as i64);
|
|
|
|
fx.bcx.ins().bitcast(types::F64, zero)
|
|
|
|
}
|
|
|
|
_ => panic!("clif_type returned {}", clif_ty),
|
|
|
|
};
|
|
|
|
fx.bcx.def_var(mir_var(var), val);
|
|
|
|
}
|
|
|
|
CPlace::Addr(_, _, _) | CPlace::Stack(_, _) => {
|
|
|
|
// Don't write to `ret`, as the destination memory is already uninitialized.
|
|
|
|
}
|
|
|
|
}
|
|
|
|
};
|
2019-02-16 13:49:42 +01:00
|
|
|
write_bytes, (c dst, v val, v count) {
|
|
|
|
let pointee_ty = dst.layout().ty.builtin_deref(true).unwrap().ty;
|
|
|
|
let pointee_size = fx.layout_of(pointee_ty).size.bytes();
|
|
|
|
let count = fx.bcx.ins().imul_imm(count, pointee_size as i64);
|
|
|
|
let dst_ptr = dst.load_scalar(fx);
|
|
|
|
fx.bcx.call_memset(fx.module.target_config(), dst_ptr, val, count);
|
2018-10-06 10:43:01 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
ctlz | ctlz_nonzero, <T> (v arg) {
|
2019-08-13 11:46:59 +02:00
|
|
|
// FIXME trap on `ctlz_nonzero` with zero arg.
|
2019-06-29 16:43:20 +02:00
|
|
|
let res = if T == fx.tcx.types.u128 || T == fx.tcx.types.i128 {
|
|
|
|
// FIXME verify this algorithm is correct
|
|
|
|
let (lsb, msb) = fx.bcx.ins().isplit(arg);
|
|
|
|
let lsb_lz = fx.bcx.ins().clz(lsb);
|
|
|
|
let msb_lz = fx.bcx.ins().clz(msb);
|
2019-07-24 17:16:31 +02:00
|
|
|
let msb_is_zero = fx.bcx.ins().icmp_imm(IntCC::Equal, msb, 0);
|
2019-06-29 16:43:20 +02:00
|
|
|
let lsb_lz_plus_64 = fx.bcx.ins().iadd_imm(lsb_lz, 64);
|
2019-07-24 17:16:31 +02:00
|
|
|
fx.bcx.ins().select(msb_is_zero, lsb_lz_plus_64, msb_lz)
|
2019-06-29 16:43:20 +02:00
|
|
|
} else {
|
|
|
|
fx.bcx.ins().clz(arg)
|
|
|
|
};
|
|
|
|
let res = CValue::by_val(res, fx.layout_of(T));
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, res);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
cttz | cttz_nonzero, <T> (v arg) {
|
2019-08-13 11:46:59 +02:00
|
|
|
// FIXME trap on `cttz_nonzero` with zero arg.
|
2019-06-29 16:43:20 +02:00
|
|
|
let res = if T == fx.tcx.types.u128 || T == fx.tcx.types.i128 {
|
|
|
|
// FIXME verify this algorithm is correct
|
|
|
|
let (lsb, msb) = fx.bcx.ins().isplit(arg);
|
|
|
|
let lsb_tz = fx.bcx.ins().ctz(lsb);
|
|
|
|
let msb_tz = fx.bcx.ins().ctz(msb);
|
2019-07-24 17:16:31 +02:00
|
|
|
let lsb_is_zero = fx.bcx.ins().icmp_imm(IntCC::Equal, lsb, 0);
|
|
|
|
let msb_tz_plus_64 = fx.bcx.ins().iadd_imm(msb_tz, 64);
|
|
|
|
fx.bcx.ins().select(lsb_is_zero, msb_tz_plus_64, lsb_tz)
|
2019-06-29 16:43:20 +02:00
|
|
|
} else {
|
|
|
|
fx.bcx.ins().ctz(arg)
|
|
|
|
};
|
|
|
|
let res = CValue::by_val(res, fx.layout_of(T));
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, res);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
ctpop, <T> (v arg) {
|
2019-06-11 16:25:07 +02:00
|
|
|
let res = CValue::by_val(fx.bcx.ins().popcnt(arg), fx.layout_of(T));
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, res);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
bitreverse, <T> (v arg) {
|
2019-06-11 16:25:07 +02:00
|
|
|
let res = CValue::by_val(fx.bcx.ins().bitrev(arg), fx.layout_of(T));
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, res);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-11-17 18:52:47 +01:00
|
|
|
bswap, <T> (v arg) {
|
|
|
|
// FIXME(CraneStation/cranelift#794) add bswap instruction to cranelift
|
|
|
|
fn swap(bcx: &mut FunctionBuilder, v: Value) -> Value {
|
|
|
|
match bcx.func.dfg.value_type(v) {
|
|
|
|
types::I8 => v,
|
|
|
|
|
|
|
|
// https://code.woboq.org/gcc/include/bits/byteswap.h.html
|
|
|
|
types::I16 => {
|
|
|
|
let tmp1 = bcx.ins().ishl_imm(v, 8);
|
|
|
|
let n1 = bcx.ins().band_imm(tmp1, 0xFF00);
|
|
|
|
|
|
|
|
let tmp2 = bcx.ins().ushr_imm(v, 8);
|
|
|
|
let n2 = bcx.ins().band_imm(tmp2, 0x00FF);
|
|
|
|
|
|
|
|
bcx.ins().bor(n1, n2)
|
|
|
|
}
|
|
|
|
types::I32 => {
|
|
|
|
let tmp1 = bcx.ins().ishl_imm(v, 24);
|
|
|
|
let n1 = bcx.ins().band_imm(tmp1, 0xFF00_0000);
|
|
|
|
|
|
|
|
let tmp2 = bcx.ins().ishl_imm(v, 8);
|
|
|
|
let n2 = bcx.ins().band_imm(tmp2, 0x00FF_0000);
|
|
|
|
|
|
|
|
let tmp3 = bcx.ins().ushr_imm(v, 8);
|
|
|
|
let n3 = bcx.ins().band_imm(tmp3, 0x0000_FF00);
|
|
|
|
|
|
|
|
let tmp4 = bcx.ins().ushr_imm(v, 24);
|
|
|
|
let n4 = bcx.ins().band_imm(tmp4, 0x0000_00FF);
|
|
|
|
|
|
|
|
let or_tmp1 = bcx.ins().bor(n1, n2);
|
|
|
|
let or_tmp2 = bcx.ins().bor(n3, n4);
|
|
|
|
bcx.ins().bor(or_tmp1, or_tmp2)
|
|
|
|
}
|
|
|
|
types::I64 => {
|
|
|
|
let tmp1 = bcx.ins().ishl_imm(v, 56);
|
|
|
|
let n1 = bcx.ins().band_imm(tmp1, 0xFF00_0000_0000_0000u64 as i64);
|
|
|
|
|
|
|
|
let tmp2 = bcx.ins().ishl_imm(v, 40);
|
|
|
|
let n2 = bcx.ins().band_imm(tmp2, 0x00FF_0000_0000_0000u64 as i64);
|
|
|
|
|
|
|
|
let tmp3 = bcx.ins().ishl_imm(v, 24);
|
|
|
|
let n3 = bcx.ins().band_imm(tmp3, 0x0000_FF00_0000_0000u64 as i64);
|
|
|
|
|
|
|
|
let tmp4 = bcx.ins().ishl_imm(v, 8);
|
|
|
|
let n4 = bcx.ins().band_imm(tmp4, 0x0000_00FF_0000_0000u64 as i64);
|
|
|
|
|
|
|
|
let tmp5 = bcx.ins().ushr_imm(v, 8);
|
|
|
|
let n5 = bcx.ins().band_imm(tmp5, 0x0000_0000_FF00_0000u64 as i64);
|
|
|
|
|
|
|
|
let tmp6 = bcx.ins().ushr_imm(v, 24);
|
|
|
|
let n6 = bcx.ins().band_imm(tmp6, 0x0000_0000_00FF_0000u64 as i64);
|
|
|
|
|
|
|
|
let tmp7 = bcx.ins().ushr_imm(v, 40);
|
|
|
|
let n7 = bcx.ins().band_imm(tmp7, 0x0000_0000_0000_FF00u64 as i64);
|
|
|
|
|
|
|
|
let tmp8 = bcx.ins().ushr_imm(v, 56);
|
|
|
|
let n8 = bcx.ins().band_imm(tmp8, 0x0000_0000_0000_00FFu64 as i64);
|
|
|
|
|
|
|
|
let or_tmp1 = bcx.ins().bor(n1, n2);
|
|
|
|
let or_tmp2 = bcx.ins().bor(n3, n4);
|
|
|
|
let or_tmp3 = bcx.ins().bor(n5, n6);
|
|
|
|
let or_tmp4 = bcx.ins().bor(n7, n8);
|
|
|
|
|
|
|
|
let or_tmp5 = bcx.ins().bor(or_tmp1, or_tmp2);
|
|
|
|
let or_tmp6 = bcx.ins().bor(or_tmp3, or_tmp4);
|
|
|
|
bcx.ins().bor(or_tmp5, or_tmp6)
|
|
|
|
}
|
2019-06-29 16:53:20 +02:00
|
|
|
types::I128 => {
|
|
|
|
let (lo, hi) = bcx.ins().isplit(v);
|
|
|
|
let lo = swap(bcx, lo);
|
|
|
|
let hi = swap(bcx, hi);
|
|
|
|
bcx.ins().iconcat(hi, lo)
|
|
|
|
}
|
|
|
|
ty => unimplemented!("bswap {}", ty),
|
2018-11-17 18:52:47 +01:00
|
|
|
}
|
|
|
|
};
|
|
|
|
let res = CValue::by_val(swap(&mut fx.bcx, arg), fx.layout_of(T));
|
|
|
|
ret.write_cvalue(fx, res);
|
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
needs_drop, <T> () {
|
|
|
|
let needs_drop = if T.needs_drop(fx.tcx, ParamEnv::reveal_all()) {
|
2018-10-03 18:21:52 +02:00
|
|
|
1
|
|
|
|
} else {
|
|
|
|
0
|
|
|
|
};
|
|
|
|
let needs_drop = CValue::const_val(fx, fx.tcx.types.bool, needs_drop);
|
|
|
|
ret.write_cvalue(fx, needs_drop);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2019-01-06 15:27:20 +01:00
|
|
|
panic_if_uninhabited, <T> () {
|
|
|
|
if fx.layout_of(T).abi.is_uninhabited() {
|
2019-03-23 13:06:35 +01:00
|
|
|
crate::trap::trap_panic(fx, "[panic] Called intrinsic::panic_if_uninhabited for uninhabited type.");
|
2019-01-06 18:11:30 +01:00
|
|
|
return;
|
2019-01-06 15:27:20 +01:00
|
|
|
}
|
|
|
|
};
|
2018-10-06 10:24:09 +02:00
|
|
|
|
2019-06-23 16:33:34 +02:00
|
|
|
volatile_load, (c ptr) {
|
|
|
|
// Cranelift treats loads as volatile by default
|
|
|
|
let inner_layout =
|
|
|
|
fx.layout_of(ptr.layout().ty.builtin_deref(true).unwrap().ty);
|
|
|
|
let val = CValue::by_ref(ptr.load_scalar(fx), inner_layout);
|
|
|
|
ret.write_cvalue(fx, val);
|
|
|
|
};
|
|
|
|
volatile_store, (v ptr, c val) {
|
|
|
|
// Cranelift treats stores as volatile by default
|
|
|
|
let dest = CPlace::for_addr(ptr, val.layout());
|
|
|
|
dest.write_cvalue(fx, val);
|
|
|
|
};
|
|
|
|
|
2018-10-05 20:11:47 +02:00
|
|
|
_ if intrinsic.starts_with("atomic_fence"), () {};
|
|
|
|
_ if intrinsic.starts_with("atomic_singlethreadfence"), () {};
|
|
|
|
_ if intrinsic.starts_with("atomic_load"), (c ptr) {
|
2018-10-03 18:21:52 +02:00
|
|
|
let inner_layout =
|
2018-10-05 19:55:06 +02:00
|
|
|
fx.layout_of(ptr.layout().ty.builtin_deref(true).unwrap().ty);
|
2019-06-11 15:32:30 +02:00
|
|
|
let val = CValue::by_ref(ptr.load_scalar(fx), inner_layout);
|
2018-10-03 18:21:52 +02:00
|
|
|
ret.write_cvalue(fx, val);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-05 20:11:47 +02:00
|
|
|
_ if intrinsic.starts_with("atomic_store"), (v ptr, c val) {
|
2019-06-11 16:30:47 +02:00
|
|
|
let dest = CPlace::for_addr(ptr, val.layout());
|
2018-10-05 19:55:06 +02:00
|
|
|
dest.write_cvalue(fx, val);
|
|
|
|
};
|
2018-10-06 10:24:09 +02:00
|
|
|
_ if intrinsic.starts_with("atomic_xchg"), <T> (v ptr, c src) {
|
|
|
|
// Read old
|
2018-11-12 07:23:39 -08:00
|
|
|
let clif_ty = fx.clif_type(T).unwrap();
|
2018-10-03 18:21:52 +02:00
|
|
|
let old = fx.bcx.ins().load(clif_ty, MemFlags::new(), ptr, 0);
|
2019-06-11 16:25:07 +02:00
|
|
|
ret.write_cvalue(fx, CValue::by_val(old, fx.layout_of(T)));
|
2018-10-06 10:24:09 +02:00
|
|
|
|
|
|
|
// Write new
|
2019-06-11 16:30:47 +02:00
|
|
|
let dest = CPlace::for_addr(ptr, src.layout());
|
2018-10-06 10:24:09 +02:00
|
|
|
dest.write_cvalue(fx, src);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2018-10-06 10:24:09 +02:00
|
|
|
_ if intrinsic.starts_with("atomic_cxchg"), <T> (v ptr, v test_old, v new) { // both atomic_cxchg_* and atomic_cxchgweak_*
|
|
|
|
// Read old
|
2018-11-12 07:23:39 -08:00
|
|
|
let clif_ty = fx.clif_type(T).unwrap();
|
2018-10-03 18:21:52 +02:00
|
|
|
let old = fx.bcx.ins().load(clif_ty, MemFlags::new(), ptr, 0);
|
2018-10-06 10:24:09 +02:00
|
|
|
|
|
|
|
// Compare
|
|
|
|
let is_eq = fx.bcx.ins().icmp(IntCC::Equal, old, test_old);
|
2019-02-16 16:24:03 +01:00
|
|
|
let new = crate::common::codegen_select(&mut fx.bcx, is_eq, new, old); // Keep old if not equal to test_old
|
2018-10-06 10:24:09 +02:00
|
|
|
|
|
|
|
// Write new
|
2018-10-03 18:21:52 +02:00
|
|
|
fx.bcx.ins().store(MemFlags::new(), new, ptr, 0);
|
2018-10-06 10:24:09 +02:00
|
|
|
|
2019-06-11 15:32:30 +02:00
|
|
|
let ret_val = CValue::by_val_pair(old, fx.bcx.ins().bint(types::I8, is_eq), ret.layout());
|
2018-10-06 10:24:09 +02:00
|
|
|
ret.write_cvalue(fx, ret_val);
|
|
|
|
};
|
|
|
|
|
|
|
|
_ if intrinsic.starts_with("atomic_xadd"), <T> (v ptr, v amount) {
|
|
|
|
atomic_binop_return_old! (fx, iadd<T>(ptr, amount) -> ret);
|
|
|
|
};
|
|
|
|
_ if intrinsic.starts_with("atomic_xsub"), <T> (v ptr, v amount) {
|
|
|
|
atomic_binop_return_old! (fx, isub<T>(ptr, amount) -> ret);
|
|
|
|
};
|
|
|
|
_ if intrinsic.starts_with("atomic_and"), <T> (v ptr, v src) {
|
|
|
|
atomic_binop_return_old! (fx, band<T>(ptr, src) -> ret);
|
|
|
|
};
|
|
|
|
_ if intrinsic.starts_with("atomic_nand"), <T> (v ptr, v src) {
|
2019-08-01 10:58:18 +02:00
|
|
|
let clif_ty = fx.clif_type(T).unwrap();
|
|
|
|
let old = fx.bcx.ins().load(clif_ty, MemFlags::new(), ptr, 0);
|
|
|
|
let and = fx.bcx.ins().band(old, src);
|
|
|
|
let new = fx.bcx.ins().bnot(and);
|
|
|
|
fx.bcx.ins().store(MemFlags::new(), new, ptr, 0);
|
|
|
|
ret.write_cvalue(fx, CValue::by_val(old, fx.layout_of(T)));
|
2018-10-06 10:24:09 +02:00
|
|
|
};
|
|
|
|
_ if intrinsic.starts_with("atomic_or"), <T> (v ptr, v src) {
|
|
|
|
atomic_binop_return_old! (fx, bor<T>(ptr, src) -> ret);
|
|
|
|
};
|
|
|
|
_ if intrinsic.starts_with("atomic_xor"), <T> (v ptr, v src) {
|
|
|
|
atomic_binop_return_old! (fx, bxor<T>(ptr, src) -> ret);
|
|
|
|
};
|
|
|
|
|
|
|
|
_ if intrinsic.starts_with("atomic_max"), <T> (v ptr, v src) {
|
|
|
|
atomic_minmax!(fx, IntCC::SignedGreaterThan, <T> (ptr, src) -> ret);
|
|
|
|
};
|
|
|
|
_ if intrinsic.starts_with("atomic_umax"), <T> (v ptr, v src) {
|
|
|
|
atomic_minmax!(fx, IntCC::UnsignedGreaterThan, <T> (ptr, src) -> ret);
|
|
|
|
};
|
|
|
|
_ if intrinsic.starts_with("atomic_min"), <T> (v ptr, v src) {
|
|
|
|
atomic_minmax!(fx, IntCC::SignedLessThan, <T> (ptr, src) -> ret);
|
|
|
|
};
|
|
|
|
_ if intrinsic.starts_with("atomic_umin"), <T> (v ptr, v src) {
|
|
|
|
atomic_minmax!(fx, IntCC::UnsignedLessThan, <T> (ptr, src) -> ret);
|
2018-10-05 19:55:06 +02:00
|
|
|
};
|
2019-07-27 17:48:24 +02:00
|
|
|
|
|
|
|
minnumf32, (v a, v b) {
|
|
|
|
let val = fx.bcx.ins().fmin(a, b);
|
|
|
|
let val = CValue::by_val(val, fx.layout_of(fx.tcx.types.f32));
|
|
|
|
ret.write_cvalue(fx, val);
|
|
|
|
};
|
|
|
|
minnumf64, (v a, v b) {
|
|
|
|
let val = fx.bcx.ins().fmin(a, b);
|
|
|
|
let val = CValue::by_val(val, fx.layout_of(fx.tcx.types.f64));
|
|
|
|
ret.write_cvalue(fx, val);
|
|
|
|
};
|
|
|
|
maxnumf32, (v a, v b) {
|
|
|
|
let val = fx.bcx.ins().fmax(a, b);
|
|
|
|
let val = CValue::by_val(val, fx.layout_of(fx.tcx.types.f32));
|
|
|
|
ret.write_cvalue(fx, val);
|
|
|
|
};
|
|
|
|
maxnumf64, (v a, v b) {
|
|
|
|
let val = fx.bcx.ins().fmax(a, b);
|
|
|
|
let val = CValue::by_val(val, fx.layout_of(fx.tcx.types.f64));
|
|
|
|
ret.write_cvalue(fx, val);
|
|
|
|
};
|
|
|
|
|
2019-07-31 09:45:11 +02:00
|
|
|
simd_cast, (c a) {
|
|
|
|
let (lane_layout, lane_count) = lane_type_and_count(fx, a.layout(), intrinsic);
|
|
|
|
let (ret_lane_layout, ret_lane_count) = lane_type_and_count(fx, ret.layout(), intrinsic);
|
|
|
|
assert_eq!(lane_count, ret_lane_count);
|
|
|
|
|
|
|
|
let ret_lane_ty = fx.clif_type(ret_lane_layout.ty).unwrap();
|
|
|
|
|
2019-08-12 17:25:16 +02:00
|
|
|
let from_signed = type_sign(lane_layout.ty);
|
|
|
|
let to_signed = type_sign(ret_lane_layout.ty);
|
2019-07-31 09:45:11 +02:00
|
|
|
|
|
|
|
for lane in 0..lane_count {
|
|
|
|
let lane = mir::Field::new(lane.try_into().unwrap());
|
|
|
|
|
|
|
|
let a_lane = a.value_field(fx, lane).load_scalar(fx);
|
2019-08-12 17:25:16 +02:00
|
|
|
let res = clif_int_or_float_cast(fx, a_lane, from_signed, ret_lane_ty, to_signed);
|
2019-07-31 09:45:11 +02:00
|
|
|
ret.place_field(fx, lane).write_cvalue(fx, CValue::by_val(res, ret_lane_layout));
|
|
|
|
}
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
|
2019-07-27 17:52:57 +02:00
|
|
|
simd_eq, (c x, c y) {
|
2019-07-28 09:45:01 +02:00
|
|
|
simd_cmp!(fx, intrinsic, Equal(x, y) -> ret);
|
2019-07-27 17:52:57 +02:00
|
|
|
};
|
|
|
|
simd_ne, (c x, c y) {
|
2019-07-28 09:45:01 +02:00
|
|
|
simd_cmp!(fx, intrinsic, NotEqual(x, y) -> ret);
|
2019-07-27 17:52:57 +02:00
|
|
|
};
|
|
|
|
simd_lt, (c x, c y) {
|
2019-07-28 09:45:01 +02:00
|
|
|
simd_cmp!(fx, intrinsic, UnsignedLessThan|SignedLessThan(x, y) -> ret);
|
2019-07-27 17:52:57 +02:00
|
|
|
};
|
|
|
|
simd_le, (c x, c y) {
|
2019-07-28 09:45:01 +02:00
|
|
|
simd_cmp!(fx, intrinsic, UnsignedLessThanOrEqual|SignedLessThanOrEqual(x, y) -> ret);
|
2019-07-27 17:52:57 +02:00
|
|
|
};
|
|
|
|
simd_gt, (c x, c y) {
|
2019-07-28 09:45:01 +02:00
|
|
|
simd_cmp!(fx, intrinsic, UnsignedGreaterThan|SignedGreaterThan(x, y) -> ret);
|
2019-07-27 17:52:57 +02:00
|
|
|
};
|
|
|
|
simd_ge, (c x, c y) {
|
2019-07-28 09:45:01 +02:00
|
|
|
simd_cmp!(fx, intrinsic, UnsignedGreaterThanOrEqual|SignedGreaterThanOrEqual(x, y) -> ret);
|
2019-07-27 17:52:57 +02:00
|
|
|
};
|
|
|
|
|
2019-07-28 10:24:57 +02:00
|
|
|
// simd_shuffle32<T, U>(x: T, y: T, idx: [u32; 32]) -> U
|
2019-07-28 11:24:33 +02:00
|
|
|
_ if intrinsic.starts_with("simd_shuffle"), (c x, c y, o idx) {
|
|
|
|
let n: u32 = intrinsic["simd_shuffle".len()..].parse().unwrap();
|
2019-07-28 10:24:57 +02:00
|
|
|
|
|
|
|
assert_eq!(x.layout(), y.layout());
|
|
|
|
let layout = x.layout();
|
|
|
|
|
|
|
|
let (lane_type, lane_count) = lane_type_and_count(fx, layout, intrinsic);
|
|
|
|
let (ret_lane_type, ret_lane_count) = lane_type_and_count(fx, ret.layout(), intrinsic);
|
|
|
|
|
|
|
|
assert_eq!(lane_type, ret_lane_type);
|
|
|
|
assert_eq!(n, ret_lane_count);
|
|
|
|
|
|
|
|
let total_len = lane_count * 2;
|
|
|
|
|
2019-07-28 11:24:33 +02:00
|
|
|
let indexes = {
|
|
|
|
use rustc::mir::interpret::*;
|
2019-07-30 14:37:20 +02:00
|
|
|
let idx_const = crate::constant::mir_operand_get_const_val(fx, idx).expect("simd_shuffle* idx not const");
|
2019-07-28 11:24:33 +02:00
|
|
|
|
|
|
|
let idx_bytes = match idx_const.val {
|
2019-08-07 12:35:49 +02:00
|
|
|
ConstValue::ByRef { alloc, offset } => {
|
2019-07-28 11:24:33 +02:00
|
|
|
let ptr = Pointer::new(AllocId(0 /* dummy */), offset);
|
|
|
|
let size = Size::from_bytes(4 * u64::from(ret_lane_count) /* size_of([u32; ret_lane_count]) */);
|
|
|
|
alloc.get_bytes(fx, ptr, size).unwrap()
|
|
|
|
}
|
|
|
|
_ => unreachable!("{:?}", idx_const),
|
|
|
|
};
|
|
|
|
|
|
|
|
(0..ret_lane_count).map(|i| {
|
|
|
|
let i = usize::try_from(i).unwrap();
|
|
|
|
let idx = rustc::mir::interpret::read_target_uint(
|
|
|
|
fx.tcx.data_layout.endian,
|
|
|
|
&idx_bytes[4*i.. 4*i + 4],
|
|
|
|
).expect("read_target_uint");
|
|
|
|
u32::try_from(idx).expect("try_from u32")
|
|
|
|
}).collect::<Vec<u32>>()
|
|
|
|
};
|
|
|
|
|
|
|
|
for &idx in &indexes {
|
|
|
|
assert!(idx < total_len, "idx {} out of range 0..{}", idx, total_len);
|
|
|
|
}
|
|
|
|
|
2019-07-29 11:23:53 +02:00
|
|
|
for (out_idx, in_idx) in indexes.into_iter().enumerate() {
|
|
|
|
let in_lane = if in_idx < lane_count {
|
|
|
|
x.value_field(fx, mir::Field::new(in_idx.try_into().unwrap()))
|
|
|
|
} else {
|
|
|
|
y.value_field(fx, mir::Field::new((in_idx - lane_count).try_into().unwrap()))
|
|
|
|
};
|
|
|
|
let out_lane = ret.place_field(fx, mir::Field::new(out_idx));
|
|
|
|
out_lane.write_cvalue(fx, in_lane);
|
|
|
|
}
|
2019-07-28 10:24:57 +02:00
|
|
|
};
|
|
|
|
|
2019-08-05 16:28:27 +02:00
|
|
|
simd_extract, (c v, o idx) {
|
|
|
|
let idx_const = crate::constant::mir_operand_get_const_val(fx, idx).expect("simd_extract* idx not const");
|
|
|
|
let idx = idx_const.val.try_to_bits(Size::from_bytes(4 /* u32*/)).expect(&format!("kind not scalar: {:?}", idx_const));
|
|
|
|
let (_lane_type, lane_count) = lane_type_and_count(fx, v.layout(), intrinsic);
|
|
|
|
if idx >= lane_count.into() {
|
|
|
|
fx.tcx.sess.span_fatal(fx.mir.span, &format!("[simd_extract] idx {} >= lane_count {}", idx, lane_count));
|
|
|
|
}
|
|
|
|
|
|
|
|
let ret_lane = v.value_field(fx, mir::Field::new(idx.try_into().unwrap()));
|
|
|
|
ret.write_cvalue(fx, ret_lane);
|
|
|
|
};
|
|
|
|
|
2019-07-27 17:48:24 +02:00
|
|
|
simd_add, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_flt_binop!(fx, intrinsic, iadd|fadd(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
simd_sub, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_flt_binop!(fx, intrinsic, isub|fsub(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
simd_mul, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_flt_binop!(fx, intrinsic, imul|fmul(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
simd_div, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_flt_binop!(fx, intrinsic, udiv|sdiv|fdiv(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
simd_shl, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_binop!(fx, intrinsic, ishl(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
simd_shr, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_binop!(fx, intrinsic, ushr|sshr(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
simd_and, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_binop!(fx, intrinsic, band(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
simd_or, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_binop!(fx, intrinsic, bor(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
2019-07-28 10:24:57 +02:00
|
|
|
simd_xor, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_int_binop!(fx, intrinsic, bxor(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
simd_fmin, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_flt_binop!(fx, intrinsic, fmin(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
|
|
|
simd_fmax, (c x, c y) {
|
2019-07-30 14:37:20 +02:00
|
|
|
simd_flt_binop!(fx, intrinsic, fmax(x, y) -> ret);
|
2019-07-27 17:48:24 +02:00
|
|
|
};
|
2019-07-31 14:04:00 +02:00
|
|
|
|
|
|
|
try, (v f, v data, v _local_ptr) {
|
|
|
|
// FIXME once unwinding is supported, change this to actually catch panics
|
|
|
|
let f_sig = fx.bcx.func.import_signature(Signature {
|
|
|
|
call_conv: cranelift::codegen::isa::CallConv::SystemV,
|
|
|
|
params: vec![AbiParam::new(fx.bcx.func.dfg.value_type(data))],
|
|
|
|
returns: vec![],
|
|
|
|
});
|
|
|
|
|
|
|
|
fx.bcx.ins().call_indirect(f_sig, f, &[data]);
|
|
|
|
|
|
|
|
let ret_val = CValue::const_val(fx, ret.layout().ty, 0);
|
|
|
|
ret.write_cvalue(fx, ret_val);
|
|
|
|
};
|
2018-10-03 18:21:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if let Some((_, dest)) = destination {
|
|
|
|
let ret_ebb = fx.get_ebb(dest);
|
|
|
|
fx.bcx.ins().jump(ret_ebb, &[]);
|
|
|
|
} else {
|
2019-03-23 13:06:35 +01:00
|
|
|
trap_unreachable(fx, "[corruption] Diverging intrinsic returned.");
|
2018-10-03 18:21:52 +02:00
|
|
|
}
|
|
|
|
}
|