338 lines
13 KiB
Makefile
338 lines
13 KiB
Makefile
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# We borrow heavily from the kernel build setup, though we are simpler since
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# we don't have Kconfig tweaking settings on us.
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# The implicit make rules have it looking for RCS files, among other things.
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# We instead explicitly write all the rules we care about.
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# It's even quicker (saves ~200ms) to pass -r on the command line.
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MAKEFLAGS=-r
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# The source directory tree.
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srcdir := ../../..
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# The name of the builddir.
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builddir_name ?= out
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# The V=1 flag on command line makes us verbosely print command lines.
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ifdef V
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quiet=
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else
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quiet=quiet_
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endif
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# Specify BUILDTYPE=Release on the command line for a release build.
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BUILDTYPE ?= Default
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# Directory all our build output goes into.
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# Note that this must be two directories beneath src/ for unit tests to pass,
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# as they reach into the src/ directory for data with relative paths.
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builddir ?= $(builddir_name)/$(BUILDTYPE)
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abs_builddir := $(abspath $(builddir))
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depsdir := $(builddir)/.deps
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# Object output directory.
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obj := $(builddir)/obj
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abs_obj := $(abspath $(obj))
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# We build up a list of every single one of the targets so we can slurp in the
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# generated dependency rule Makefiles in one pass.
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all_deps :=
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# C++ apps need to be linked with g++. Not sure what's appropriate.
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#
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# Note, the flock is used to seralize linking. Linking is a memory-intensive
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# process so running parallel links can often lead to thrashing. To disable
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# the serialization, override FLOCK via an envrionment variable as follows:
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#
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# export FLOCK=
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#
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# This will allow make to invoke N linker processes as specified in -jN.
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FLOCK ?= flock $(builddir)/linker.lock
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LINK ?= $(FLOCK) $(CXX)
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CC.target ?= $(CC)
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CFLAGS.target ?= $(CFLAGS)
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CXX.target ?= $(CXX)
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CXXFLAGS.target ?= $(CXXFLAGS)
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LINK.target ?= $(LINK)
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LDFLAGS.target ?= $(LDFLAGS)
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AR.target ?= $(AR)
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ARFLAGS.target ?= crsT
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# N.B.: the logic of which commands to run should match the computation done
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# in gyp's make.py where ARFLAGS.host etc. is computed.
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# TODO(evan): move all cross-compilation logic to gyp-time so we don't need
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# to replicate this environment fallback in make as well.
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CC.host ?= gcc
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CFLAGS.host ?=
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CXX.host ?= g++
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CXXFLAGS.host ?=
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LINK.host ?= g++
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LDFLAGS.host ?=
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AR.host ?= ar
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ARFLAGS.host := crsT
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# Define a dir function that can handle spaces.
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# http://www.gnu.org/software/make/manual/make.html#Syntax-of-Functions
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# "leading spaces cannot appear in the text of the first argument as written.
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# These characters can be put into the argument value by variable substitution."
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empty :=
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space := $(empty) $(empty)
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# http://stackoverflow.com/questions/1189781/using-make-dir-or-notdir-on-a-path-with-spaces
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replace_spaces = $(subst $(space),?,$1)
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unreplace_spaces = $(subst ?,$(space),$1)
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dirx = $(call unreplace_spaces,$(dir $(call replace_spaces,$1)))
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# Flags to make gcc output dependency info. Note that you need to be
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# careful here to use the flags that ccache and distcc can understand.
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# We write to a dep file on the side first and then rename at the end
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# so we can't end up with a broken dep file.
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depfile = $(depsdir)/$(call replace_spaces,$@).d
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DEPFLAGS = -MMD -MF $(depfile).raw
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# We have to fixup the deps output in a few ways.
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# (1) the file output should mention the proper .o file.
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# ccache or distcc lose the path to the target, so we convert a rule of
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# the form:
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# foobar.o: DEP1 DEP2
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# into
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# path/to/foobar.o: DEP1 DEP2
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# (2) we want missing files not to cause us to fail to build.
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# We want to rewrite
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# foobar.o: DEP1 DEP2 \
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# DEP3
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# to
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# DEP1:
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# DEP2:
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# DEP3:
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# so if the files are missing, they're just considered phony rules.
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# We have to do some pretty insane escaping to get those backslashes
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# and dollar signs past make, the shell, and sed at the same time.
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# Doesn't work with spaces, but that's fine: .d files have spaces in
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# their names replaced with other characters.
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define fixup_dep
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# The depfile may not exist if the input file didn't have any #includes.
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touch $(depfile).raw
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# Fixup path as in (1).
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sed -e "s|^$(notdir $@)|$@|" $(depfile).raw >> $(depfile)
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# Add extra rules as in (2).
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# We remove slashes and replace spaces with new lines;
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# remove blank lines;
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# delete the first line and append a colon to the remaining lines.
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sed -e 's|\\||' -e 'y| |\n|' $(depfile).raw |\
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grep -v '^$$' |\
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sed -e 1d -e 's|$$|:|' \
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>> $(depfile)
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rm $(depfile).raw
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endef
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# Command definitions:
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# - cmd_foo is the actual command to run;
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# - quiet_cmd_foo is the brief-output summary of the command.
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quiet_cmd_cc = CC($(TOOLSET)) $@
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cmd_cc = $(CC.$(TOOLSET)) $(GYP_CFLAGS) $(DEPFLAGS) $(CFLAGS.$(TOOLSET)) -c -o $@ $<
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quiet_cmd_cxx = CXX($(TOOLSET)) $@
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cmd_cxx = $(CXX.$(TOOLSET)) $(GYP_CXXFLAGS) $(DEPFLAGS) $(CXXFLAGS.$(TOOLSET)) -c -o $@ $<
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quiet_cmd_touch = TOUCH $@
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cmd_touch = touch $@
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quiet_cmd_copy = COPY $@
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# send stderr to /dev/null to ignore messages when linking directories.
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cmd_copy = ln -f "$<" "$@" 2>/dev/null || (rm -rf "$@" && cp -af "$<" "$@")
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quiet_cmd_alink = AR($(TOOLSET)) $@
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cmd_alink = rm -f $@ && $(AR.$(TOOLSET)) $(ARFLAGS.$(TOOLSET)) $@ $(filter %.o,$^)
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# Due to circular dependencies between libraries :(, we wrap the
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# special "figure out circular dependencies" flags around the entire
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# input list during linking.
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quiet_cmd_link = LINK($(TOOLSET)) $@
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cmd_link = $(LINK.$(TOOLSET)) $(GYP_LDFLAGS) $(LDFLAGS.$(TOOLSET)) -o $@ -Wl,--start-group $(LD_INPUTS) -Wl,--end-group $(LIBS)
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# We support two kinds of shared objects (.so):
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# 1) shared_library, which is just bundling together many dependent libraries
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# into a link line.
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# 2) loadable_module, which is generating a module intended for dlopen().
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#
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# They differ only slightly:
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# In the former case, we want to package all dependent code into the .so.
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# In the latter case, we want to package just the API exposed by the
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# outermost module.
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# This means shared_library uses --whole-archive, while loadable_module doesn't.
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# (Note that --whole-archive is incompatible with the --start-group used in
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# normal linking.)
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# Other shared-object link notes:
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# - Set SONAME to the library filename so our binaries don't reference
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# the local, absolute paths used on the link command-line.
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quiet_cmd_solink = SOLINK($(TOOLSET)) $@
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cmd_solink = $(LINK.$(TOOLSET)) -shared $(GYP_LDFLAGS) $(LDFLAGS.$(TOOLSET)) -Wl,-soname=$(@F) -o $@ -Wl,--whole-archive $(LD_INPUTS) -Wl,--no-whole-archive $(LIBS)
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quiet_cmd_solink_module = SOLINK_MODULE($(TOOLSET)) $@
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cmd_solink_module = $(LINK.$(TOOLSET)) -shared $(GYP_LDFLAGS) $(LDFLAGS.$(TOOLSET)) -Wl,-soname=$(@F) -o $@ -Wl,--start-group $(filter-out FORCE_DO_CMD, $^) -Wl,--end-group $(LIBS)
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# Define an escape_quotes function to escape single quotes.
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# This allows us to handle quotes properly as long as we always use
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# use single quotes and escape_quotes.
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escape_quotes = $(subst ','\'',$(1))
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# This comment is here just to include a ' to unconfuse syntax highlighting.
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# Define an escape_vars function to escape '$' variable syntax.
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# This allows us to read/write command lines with shell variables (e.g.
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# $LD_LIBRARY_PATH), without triggering make substitution.
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escape_vars = $(subst $$,$$$$,$(1))
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# Helper that expands to a shell command to echo a string exactly as it is in
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# make. This uses printf instead of echo because printf's behaviour with respect
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# to escape sequences is more portable than echo's across different shells
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# (e.g., dash, bash).
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exact_echo = printf '%s\n' '$(call escape_quotes,$(1))'
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# Helper to compare the command we're about to run against the command
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# we logged the last time we ran the command. Produces an empty
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# string (false) when the commands match.
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# Tricky point: Make has no string-equality test function.
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# The kernel uses the following, but it seems like it would have false
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# positives, where one string reordered its arguments.
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# arg_check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
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# $(filter-out $(cmd_$@), $(cmd_$(1))))
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# We instead substitute each for the empty string into the other, and
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# say they're equal if both substitutions produce the empty string.
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# .d files contain ? instead of spaces, take that into account.
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command_changed = $(or $(subst $(cmd_$(1)),,$(cmd_$(call replace_spaces,$@))),\
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$(subst $(cmd_$(call replace_spaces,$@)),,$(cmd_$(1))))
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# Helper that is non-empty when a prerequisite changes.
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# Normally make does this implicitly, but we force rules to always run
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# so we can check their command lines.
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# $? -- new prerequisites
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# $| -- order-only dependencies
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prereq_changed = $(filter-out FORCE_DO_CMD,$(filter-out $|,$?))
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# do_cmd: run a command via the above cmd_foo names, if necessary.
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# Should always run for a given target to handle command-line changes.
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# Second argument, if non-zero, makes it do asm/C/C++ dependency munging.
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# Third argument, if non-zero, makes it do POSTBUILDS processing.
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# Note: We intentionally do NOT call dirx for depfile, since it contains ? for
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# spaces already and dirx strips the ? characters.
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define do_cmd
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$(if $(or $(command_changed),$(prereq_changed)),
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@$(call exact_echo, $($(quiet)cmd_$(1)))
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@mkdir -p "$(call dirx,$@)" "$(dir $(depfile))"
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$(if $(findstring flock,$(word 1,$(cmd_$1))),
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@$(cmd_$(1))
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@echo " $(quiet_cmd_$(1)): Finished",
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@$(cmd_$(1))
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)
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@$(call exact_echo,$(call escape_vars,cmd_$(call replace_spaces,$@) := $(cmd_$(1)))) > $(depfile)
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@$(if $(2),$(fixup_dep))
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$(if $(and $(3), $(POSTBUILDS)),
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@for p in $(POSTBUILDS); do eval $$p; done
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)
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)
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endef
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# Declare "all" target first so it is the default, even though we don't have the
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# deps yet.
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.PHONY: all
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all:
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# Use FORCE_DO_CMD to force a target to run. Should be coupled with
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# do_cmd.
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.PHONY: FORCE_DO_CMD
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FORCE_DO_CMD:
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TOOLSET := target
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# Suffix rules, putting all outputs into $(obj).
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$(obj).$(TOOLSET)/%.o: $(srcdir)/%.c FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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$(obj).$(TOOLSET)/%.o: $(srcdir)/%.cc FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(srcdir)/%.cpp FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(srcdir)/%.cxx FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(srcdir)/%.S FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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$(obj).$(TOOLSET)/%.o: $(srcdir)/%.s FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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# Try building from generated source, too.
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$(obj).$(TOOLSET)/%.o: $(obj).$(TOOLSET)/%.c FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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$(obj).$(TOOLSET)/%.o: $(obj).$(TOOLSET)/%.cc FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(obj).$(TOOLSET)/%.cpp FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(obj).$(TOOLSET)/%.cxx FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(obj).$(TOOLSET)/%.S FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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$(obj).$(TOOLSET)/%.o: $(obj).$(TOOLSET)/%.s FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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$(obj).$(TOOLSET)/%.o: $(obj)/%.c FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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$(obj).$(TOOLSET)/%.o: $(obj)/%.cc FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(obj)/%.cpp FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(obj)/%.cxx FORCE_DO_CMD
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@$(call do_cmd,cxx,1)
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$(obj).$(TOOLSET)/%.o: $(obj)/%.S FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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$(obj).$(TOOLSET)/%.o: $(obj)/%.s FORCE_DO_CMD
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@$(call do_cmd,cc,1)
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ifeq ($(strip $(foreach prefix,$(NO_LOAD),\
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$(findstring $(join ^,$(prefix)),\
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$(join ^,src/rt/libuv/run-benchmarks.target.mk)))),)
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include src/rt/libuv/run-benchmarks.target.mk
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endif
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ifeq ($(strip $(foreach prefix,$(NO_LOAD),\
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$(findstring $(join ^,$(prefix)),\
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$(join ^,src/rt/libuv/run-tests.target.mk)))),)
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include src/rt/libuv/run-tests.target.mk
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endif
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ifeq ($(strip $(foreach prefix,$(NO_LOAD),\
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$(findstring $(join ^,$(prefix)),\
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$(join ^,src/rt/libuv/uv.target.mk)))),)
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include src/rt/libuv/uv.target.mk
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endif
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quiet_cmd_regen_makefile = ACTION Regenerating $@
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cmd_regen_makefile = ./src/rt/libuv/build/gyp/gyp -fmake --ignore-environment "--toplevel-dir=." "--depth=." "--generator-output=mk/libuv/win" "-Dlibrary=static_library" "-Dtarget_arch=ia32" "-DOS=win" src/rt/libuv/uv.gyp
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#Makefile: $(srcdir)/src/rt/libuv/uv.gyp
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# $(call do_cmd,regen_makefile)
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# "all" is a concatenation of the "all" targets from all the included
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# sub-makefiles. This is just here to clarify.
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all:
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# Add in dependency-tracking rules. $(all_deps) is the list of every single
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||
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# target in our tree. Only consider the ones with .d (dependency) info:
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||
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d_files := $(wildcard $(foreach f,$(all_deps),$(depsdir)/$(f).d))
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||
|
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ifneq ($(d_files),)
|
||
|
|
# Rather than include each individual .d file, concatenate them into a
|
||
|
|
# single file which make is able to load faster. We split this into
|
||
|
|
# commands that take 1000 files at a time to avoid overflowing the
|
||
|
|
# command line.
|
||
|
|
$(shell cat $(wordlist 1,1000,$(d_files)) > $(depsdir)/all.deps)
|
||
|
|
|
||
|
|
ifneq ($(word 1001,$(d_files)),)
|
||
|
|
$(error Found unprocessed dependency files (gyp didn't generate enough rules!))
|
||
|
|
endif
|
||
|
|
|
||
|
|
# make looks for ways to re-generate included makefiles, but in our case, we
|
||
|
|
# don't have a direct way. Explicitly telling make that it has nothing to do
|
||
|
|
# for them makes it go faster.
|
||
|
|
$(depsdir)/all.deps: ;
|
||
|
|
|
||
|
|
include $(depsdir)/all.deps
|
||
|
|
endif
|