2021-12-13 14:40:17 -06:00
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//! Codegen of `asm!` invocations.
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2020-09-23 08:13:49 -05:00
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2020-07-10 07:45:45 -05:00
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use crate::prelude::*;
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use std::fmt::Write;
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2020-08-28 05:10:48 -05:00
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use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
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2020-07-10 07:45:45 -05:00
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use rustc_middle::mir::InlineAsmOperand;
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use rustc_target::asm::*;
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pub(crate) fn codegen_inline_asm<'tcx>(
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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2020-07-10 07:45:45 -05:00
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_span: Span,
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template: &[InlineAsmTemplatePiece],
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operands: &[InlineAsmOperand<'tcx>],
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options: InlineAsmOptions,
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) {
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// FIXME add .eh_frame unwind info directives
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if template.is_empty() {
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// Black box
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return;
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2021-03-29 03:45:09 -05:00
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} else if template[0] == InlineAsmTemplatePiece::String("int $$0x29".to_string()) {
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let true_ = fx.bcx.ins().iconst(types::I32, 1);
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fx.bcx.ins().trapnz(true_, TrapCode::User(1));
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return;
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2021-05-27 06:08:14 -05:00
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} else if template[0] == InlineAsmTemplatePiece::String("movq %rbx, ".to_string())
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&& matches!(
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template[1],
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InlineAsmTemplatePiece::Placeholder { operand_idx: 0, modifier: Some('r'), span: _ }
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)
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&& template[2] == InlineAsmTemplatePiece::String("\n".to_string())
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&& template[3] == InlineAsmTemplatePiece::String("cpuid".to_string())
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&& template[4] == InlineAsmTemplatePiece::String("\n".to_string())
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&& template[5] == InlineAsmTemplatePiece::String("xchgq %rbx, ".to_string())
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&& matches!(
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template[6],
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InlineAsmTemplatePiece::Placeholder { operand_idx: 0, modifier: Some('r'), span: _ }
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)
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2021-04-30 07:49:58 -05:00
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{
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assert_eq!(operands.len(), 4);
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let (leaf, eax_place) = match operands[1] {
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InlineAsmOperand::InOut { reg, late: true, ref in_value, out_place } => {
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let reg = expect_reg(reg);
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assert_eq!(reg, InlineAsmReg::X86(X86InlineAsmReg::ax));
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(
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crate::base::codegen_operand(fx, in_value).load_scalar(fx),
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crate::base::codegen_place(fx, out_place.unwrap()),
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)
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}
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_ => unreachable!(),
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};
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let ebx_place = match operands[0] {
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InlineAsmOperand::Out { reg, late: true, place } => {
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assert_eq!(
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reg,
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InlineAsmRegOrRegClass::RegClass(InlineAsmRegClass::X86(
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X86InlineAsmRegClass::reg
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))
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);
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2021-04-30 07:49:58 -05:00
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crate::base::codegen_place(fx, place.unwrap())
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}
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_ => unreachable!(),
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};
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let (sub_leaf, ecx_place) = match operands[2] {
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InlineAsmOperand::InOut { reg, late: true, ref in_value, out_place } => {
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let reg = expect_reg(reg);
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assert_eq!(reg, InlineAsmReg::X86(X86InlineAsmReg::cx));
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(
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crate::base::codegen_operand(fx, in_value).load_scalar(fx),
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crate::base::codegen_place(fx, out_place.unwrap()),
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)
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}
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_ => unreachable!(),
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};
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let edx_place = match operands[3] {
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InlineAsmOperand::Out { reg, late: true, place } => {
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let reg = expect_reg(reg);
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assert_eq!(reg, InlineAsmReg::X86(X86InlineAsmReg::dx));
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crate::base::codegen_place(fx, place.unwrap())
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}
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_ => unreachable!(),
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};
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let (eax, ebx, ecx, edx) = crate::intrinsics::codegen_cpuid_call(fx, leaf, sub_leaf);
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eax_place.write_cvalue(fx, CValue::by_val(eax, fx.layout_of(fx.tcx.types.u32)));
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ebx_place.write_cvalue(fx, CValue::by_val(ebx, fx.layout_of(fx.tcx.types.u32)));
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ecx_place.write_cvalue(fx, CValue::by_val(ecx, fx.layout_of(fx.tcx.types.u32)));
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edx_place.write_cvalue(fx, CValue::by_val(edx, fx.layout_of(fx.tcx.types.u32)));
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return;
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} else if fx.tcx.symbol_name(fx.instance).name.starts_with("___chkstk") {
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// ___chkstk, ___chkstk_ms and __alloca are only used on Windows
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crate::trap::trap_unimplemented(fx, "Stack probes are not supported");
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} else if fx.tcx.symbol_name(fx.instance).name == "__alloca" {
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crate::trap::trap_unimplemented(fx, "Alloca is not supported");
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2020-07-10 07:45:45 -05:00
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}
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let mut slot_size = Size::from_bytes(0);
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let mut clobbered_regs = Vec::new();
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let mut inputs = Vec::new();
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let mut outputs = Vec::new();
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let mut new_slot = |reg_class: InlineAsmRegClass| {
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let reg_size = reg_class
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.supported_types(InlineAsmArch::X86_64)
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.iter()
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.map(|(ty, _)| ty.size())
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.max()
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.unwrap();
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let align = rustc_target::abi::Align::from_bytes(reg_size.bytes()).unwrap();
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slot_size = slot_size.align_to(align);
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let offset = slot_size;
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slot_size += reg_size;
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offset
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};
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// FIXME overlap input and output slots to save stack space
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for operand in operands {
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match *operand {
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InlineAsmOperand::In { reg, ref value } => {
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let reg = expect_reg(reg);
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clobbered_regs.push((reg, new_slot(reg.reg_class())));
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2020-08-28 05:10:48 -05:00
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inputs.push((
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reg,
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new_slot(reg.reg_class()),
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2020-11-03 04:00:04 -06:00
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crate::base::codegen_operand(fx, value).load_scalar(fx),
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2020-08-28 05:10:48 -05:00
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));
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2020-07-10 07:45:45 -05:00
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}
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2021-03-05 12:12:59 -06:00
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InlineAsmOperand::Out { reg, late: _, place } => {
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2020-07-10 07:45:45 -05:00
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let reg = expect_reg(reg);
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clobbered_regs.push((reg, new_slot(reg.reg_class())));
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if let Some(place) = place {
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2020-08-28 05:10:48 -05:00
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outputs.push((
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reg,
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new_slot(reg.reg_class()),
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2020-11-03 04:00:04 -06:00
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crate::base::codegen_place(fx, place),
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2020-08-28 05:10:48 -05:00
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));
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2020-07-10 07:45:45 -05:00
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}
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}
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2021-03-05 12:12:59 -06:00
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InlineAsmOperand::InOut { reg, late: _, ref in_value, out_place } => {
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2020-07-10 07:45:45 -05:00
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let reg = expect_reg(reg);
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clobbered_regs.push((reg, new_slot(reg.reg_class())));
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2020-08-28 05:10:48 -05:00
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inputs.push((
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reg,
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new_slot(reg.reg_class()),
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2020-11-03 04:00:04 -06:00
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crate::base::codegen_operand(fx, in_value).load_scalar(fx),
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2020-08-28 05:10:48 -05:00
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));
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2020-07-10 07:45:45 -05:00
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if let Some(out_place) = out_place {
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2020-08-28 05:10:48 -05:00
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outputs.push((
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reg,
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new_slot(reg.reg_class()),
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2020-11-03 04:00:04 -06:00
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crate::base::codegen_place(fx, out_place),
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2020-08-28 05:10:48 -05:00
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));
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2020-07-10 07:45:45 -05:00
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}
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}
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InlineAsmOperand::Const { value: _ } => todo!(),
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InlineAsmOperand::SymFn { value: _ } => todo!(),
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InlineAsmOperand::SymStatic { def_id: _ } => todo!(),
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}
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}
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2020-07-23 05:37:03 -05:00
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let inline_asm_index = fx.inline_asm_index;
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fx.inline_asm_index += 1;
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2021-04-30 07:49:58 -05:00
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let asm_name = format!("{}__inline_asm_{}", fx.symbol_name, inline_asm_index);
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2020-07-10 07:45:45 -05:00
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2020-08-28 05:10:48 -05:00
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let generated_asm = generate_asm_wrapper(
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&asm_name,
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InlineAsmArch::X86_64,
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options,
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template,
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clobbered_regs,
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&inputs,
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&outputs,
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);
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2020-08-22 09:17:58 -05:00
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fx.cx.global_asm.push_str(&generated_asm);
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2020-07-10 07:45:45 -05:00
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call_inline_asm(fx, &asm_name, slot_size, inputs, outputs);
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}
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fn generate_asm_wrapper(
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asm_name: &str,
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arch: InlineAsmArch,
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options: InlineAsmOptions,
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template: &[InlineAsmTemplatePiece],
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clobbered_regs: Vec<(InlineAsmReg, Size)>,
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inputs: &[(InlineAsmReg, Size, Value)],
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outputs: &[(InlineAsmReg, Size, CPlace<'_>)],
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) -> String {
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let mut generated_asm = String::new();
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writeln!(generated_asm, ".globl {}", asm_name).unwrap();
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writeln!(generated_asm, ".type {},@function", asm_name).unwrap();
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2021-03-05 12:12:59 -06:00
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writeln!(generated_asm, ".section .text.{},\"ax\",@progbits", asm_name).unwrap();
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2020-07-10 07:45:45 -05:00
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writeln!(generated_asm, "{}:", asm_name).unwrap();
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generated_asm.push_str(".intel_syntax noprefix\n");
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generated_asm.push_str(" push rbp\n");
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generated_asm.push_str(" mov rbp,rdi\n");
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// Save clobbered registers
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if !options.contains(InlineAsmOptions::NORETURN) {
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// FIXME skip registers saved by the calling convention
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for &(reg, offset) in &clobbered_regs {
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save_register(&mut generated_asm, arch, reg, offset);
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}
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}
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// Write input registers
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for &(reg, offset, _value) in inputs {
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restore_register(&mut generated_asm, arch, reg, offset);
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}
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if options.contains(InlineAsmOptions::ATT_SYNTAX) {
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generated_asm.push_str(".att_syntax\n");
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}
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// The actual inline asm
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for piece in template {
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match piece {
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InlineAsmTemplatePiece::String(s) => {
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generated_asm.push_str(s);
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}
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2021-03-05 12:12:59 -06:00
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InlineAsmTemplatePiece::Placeholder { operand_idx: _, modifier: _, span: _ } => todo!(),
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2020-07-10 07:45:45 -05:00
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}
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}
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generated_asm.push('\n');
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if options.contains(InlineAsmOptions::ATT_SYNTAX) {
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generated_asm.push_str(".intel_syntax noprefix\n");
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}
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if !options.contains(InlineAsmOptions::NORETURN) {
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// Read output registers
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for &(reg, offset, _place) in outputs {
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save_register(&mut generated_asm, arch, reg, offset);
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}
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// Restore clobbered registers
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for &(reg, offset) in clobbered_regs.iter().rev() {
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restore_register(&mut generated_asm, arch, reg, offset);
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}
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generated_asm.push_str(" pop rbp\n");
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generated_asm.push_str(" ret\n");
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} else {
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generated_asm.push_str(" ud2\n");
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}
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generated_asm.push_str(".att_syntax\n");
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2020-08-28 05:10:48 -05:00
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writeln!(generated_asm, ".size {name}, .-{name}", name = asm_name).unwrap();
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2020-07-10 07:45:45 -05:00
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generated_asm.push_str(".text\n");
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generated_asm.push_str("\n\n");
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generated_asm
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}
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fn call_inline_asm<'tcx>(
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2021-03-05 12:12:59 -06:00
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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2020-07-10 07:45:45 -05:00
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asm_name: &str,
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slot_size: Size,
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inputs: Vec<(InlineAsmReg, Size, Value)>,
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outputs: Vec<(InlineAsmReg, Size, CPlace<'tcx>)>,
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) {
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let stack_slot = fx.bcx.func.create_stack_slot(StackSlotData {
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kind: StackSlotKind::ExplicitSlot,
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offset: None,
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size: u32::try_from(slot_size.bytes()).unwrap(),
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});
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2021-03-29 03:45:09 -05:00
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if fx.clif_comments.enabled() {
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fx.add_comment(stack_slot, "inline asm scratch slot");
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}
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2020-07-10 07:45:45 -05:00
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2020-08-28 05:10:48 -05:00
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let inline_asm_func = fx
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.module
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.declare_function(
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asm_name,
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Linkage::Import,
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&Signature {
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call_conv: CallConv::SystemV,
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params: vec![AbiParam::new(fx.pointer_type)],
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returns: vec![],
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},
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)
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.unwrap();
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2021-04-30 07:49:58 -05:00
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let inline_asm_func = fx.module.declare_func_in_func(inline_asm_func, &mut fx.bcx.func);
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2021-03-29 03:45:09 -05:00
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if fx.clif_comments.enabled() {
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fx.add_comment(inline_asm_func, asm_name);
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}
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2020-07-10 07:45:45 -05:00
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for (_reg, offset, value) in inputs {
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2021-03-05 12:12:59 -06:00
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fx.bcx.ins().stack_store(value, stack_slot, i32::try_from(offset.bytes()).unwrap());
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2020-07-10 07:45:45 -05:00
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}
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let stack_slot_addr = fx.bcx.ins().stack_addr(fx.pointer_type, stack_slot, 0);
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fx.bcx.ins().call(inline_asm_func, &[stack_slot_addr]);
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for (_reg, offset, place) in outputs {
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let ty = fx.clif_type(place.layout().ty).unwrap();
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2021-03-05 12:12:59 -06:00
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let value = fx.bcx.ins().stack_load(ty, stack_slot, i32::try_from(offset.bytes()).unwrap());
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2020-07-10 07:45:45 -05:00
|
|
|
place.write_cvalue(fx, CValue::by_val(value, place.layout()));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn expect_reg(reg_or_class: InlineAsmRegOrRegClass) -> InlineAsmReg {
|
|
|
|
match reg_or_class {
|
|
|
|
InlineAsmRegOrRegClass::Reg(reg) => reg,
|
|
|
|
InlineAsmRegOrRegClass::RegClass(class) => unimplemented!("{:?}", class),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn save_register(generated_asm: &mut String, arch: InlineAsmArch, reg: InlineAsmReg, offset: Size) {
|
|
|
|
match arch {
|
|
|
|
InlineAsmArch::X86_64 => {
|
|
|
|
write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap();
|
2021-03-05 12:12:59 -06:00
|
|
|
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
|
2020-07-10 07:45:45 -05:00
|
|
|
generated_asm.push('\n');
|
|
|
|
}
|
|
|
|
_ => unimplemented!("save_register for {:?}", arch),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-08-28 05:10:48 -05:00
|
|
|
fn restore_register(
|
|
|
|
generated_asm: &mut String,
|
|
|
|
arch: InlineAsmArch,
|
|
|
|
reg: InlineAsmReg,
|
|
|
|
offset: Size,
|
|
|
|
) {
|
2020-07-10 07:45:45 -05:00
|
|
|
match arch {
|
|
|
|
InlineAsmArch::X86_64 => {
|
|
|
|
generated_asm.push_str(" mov ");
|
2021-03-05 12:12:59 -06:00
|
|
|
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
|
2020-07-10 07:45:45 -05:00
|
|
|
writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap();
|
|
|
|
}
|
|
|
|
_ => unimplemented!("restore_register for {:?}", arch),
|
|
|
|
}
|
|
|
|
}
|