2020-01-10 13:15:16 -06:00
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//! A pass that propagates the unreachable terminator of a block to its predecessors
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//! when all of their successors are unreachable. This is achieved through a
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//! post-order traversal of the blocks.
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2020-12-31 18:53:25 -06:00
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use crate::simplify;
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use crate::MirPass;
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2020-03-29 10:19:48 -05:00
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use rustc_data_structures::fx::{FxHashMap, FxHashSet};
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2020-03-29 09:41:09 -05:00
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use rustc_middle::mir::*;
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use rustc_middle::ty::TyCtxt;
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2020-01-10 13:15:16 -06:00
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pub struct UnreachablePropagation;
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impl MirPass<'_> for UnreachablePropagation {
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2020-10-04 13:01:38 -05:00
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fn run_pass<'tcx>(&self, tcx: TyCtxt<'tcx>, body: &mut Body<'tcx>) {
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2021-03-03 15:30:42 -06:00
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if tcx.sess.mir_opt_level() < 4 {
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// Enable only under -Zmir-opt-level=4 as in some cases (check the deeply-nested-opt
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2020-01-10 13:15:16 -06:00
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// perf benchmark) LLVM may spend quite a lot of time optimizing the generated code.
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return;
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}
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let mut unreachable_blocks = FxHashSet::default();
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let mut replacements = FxHashMap::default();
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for (bb, bb_data) in traversal::postorder(body) {
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let terminator = bb_data.terminator();
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// HACK: If the block contains any asm statement it is not regarded as unreachable.
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// This is a temporary solution that handles possibly diverging asm statements.
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// Accompanying testcases: mir-opt/unreachable_asm.rs and mir-opt/unreachable_asm_2.rs
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let asm_stmt_in_block = || {
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2021-11-05 19:31:32 -05:00
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bb_data.statements.iter().any(|stmt: &Statement<'_>| {
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matches!(stmt.kind, StatementKind::LlvmInlineAsm(..))
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2020-01-10 13:15:16 -06:00
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})
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};
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if terminator.kind == TerminatorKind::Unreachable && !asm_stmt_in_block() {
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unreachable_blocks.insert(bb);
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} else {
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let is_unreachable = |succ: BasicBlock| unreachable_blocks.contains(&succ);
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let terminator_kind_opt = remove_successors(&terminator.kind, is_unreachable);
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if let Some(terminator_kind) = terminator_kind_opt {
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if terminator_kind == TerminatorKind::Unreachable && !asm_stmt_in_block() {
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unreachable_blocks.insert(bb);
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}
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replacements.insert(bb, terminator_kind);
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}
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}
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}
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let replaced = !replacements.is_empty();
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for (bb, terminator_kind) in replacements {
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2020-11-18 18:16:23 -06:00
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if !tcx.consider_optimizing(|| {
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format!("UnreachablePropagation {:?} ", body.source.def_id())
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}) {
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break;
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}
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2020-01-10 13:15:16 -06:00
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body.basic_blocks_mut()[bb].terminator_mut().kind = terminator_kind;
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}
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if replaced {
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2021-05-01 16:56:48 -05:00
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simplify::remove_dead_blocks(tcx, body);
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2020-01-10 13:15:16 -06:00
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}
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}
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}
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fn remove_successors<F>(
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terminator_kind: &TerminatorKind<'tcx>,
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predicate: F,
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) -> Option<TerminatorKind<'tcx>>
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where
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F: Fn(BasicBlock) -> bool,
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{
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2020-08-13 16:59:47 -05:00
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let terminator = match *terminator_kind {
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TerminatorKind::Goto { target } if predicate(target) => TerminatorKind::Unreachable,
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2020-10-10 10:36:04 -05:00
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TerminatorKind::SwitchInt { ref discr, switch_ty, ref targets } => {
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let otherwise = targets.otherwise();
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let original_targets_len = targets.iter().len() + 1;
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2020-08-13 16:59:47 -05:00
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let (mut values, mut targets): (Vec<_>, Vec<_>) =
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2020-10-10 10:36:04 -05:00
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targets.iter().filter(|(_, bb)| !predicate(*bb)).unzip();
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2020-01-10 13:15:16 -06:00
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2020-10-10 10:36:04 -05:00
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if !predicate(otherwise) {
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targets.push(otherwise);
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2020-01-10 13:15:16 -06:00
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} else {
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values.pop();
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}
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let retained_targets_len = targets.len();
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if targets.is_empty() {
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2020-08-13 16:59:47 -05:00
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TerminatorKind::Unreachable
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2020-01-10 13:15:16 -06:00
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} else if targets.len() == 1 {
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2020-08-13 16:59:47 -05:00
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TerminatorKind::Goto { target: targets[0] }
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2020-01-10 13:15:16 -06:00
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} else if original_targets_len != retained_targets_len {
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2020-08-13 16:59:47 -05:00
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TerminatorKind::SwitchInt {
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2020-01-10 13:15:16 -06:00
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discr: discr.clone(),
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switch_ty,
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2020-10-10 10:36:04 -05:00
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targets: SwitchTargets::new(
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values.iter().copied().zip(targets.iter().copied()),
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*targets.last().unwrap(),
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),
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2020-08-13 16:59:47 -05:00
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}
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2020-01-10 13:15:16 -06:00
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} else {
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2020-08-13 16:59:47 -05:00
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return None;
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2020-01-10 13:15:16 -06:00
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}
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}
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2020-08-13 16:59:47 -05:00
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_ => return None,
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};
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Some(terminator)
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2020-01-10 13:15:16 -06:00
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}
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