rust/.gitignore

target
**/*.rs.bk
*.rlib
*.o
perf.data
perf.data.old
*.events
*.string*
/build_sysroot/sysroot
/build_sysroot/sysroot_src
/build_sysroot/Cargo.lock
/build_sysroot/test_target/Cargo.lock
/rust
/simple-raytracer
/regex
gimple*
*asm
res
test-backend
gcc_path
Initial commit 2020-05-10 09:54:30 -05:00			`target`
			`*/.rs.bk`
			`*.rlib`
			`*.o`
			`perf.data`
			`perf.data.old`
			`*.events`
			`.string`
			`/build_sysroot/sysroot`
Implement basic inline asm support (#72) * Implement basic support for inline assembly * Disable LTO We don't support it yet at all * Handle `inout(reg) var` correctly Turns out that `+` readwrite output registers cannot be tied with input variables. * Add limited support for llvm_asm! * Handle CHANNEL correctly * Add support for arbitrary explicit registers * Handle symbols properly * Add rudimentary asm tests * Exclude llvm_asm! tests from tests runs * Insert `__builtin_unreachable()` after diverging asm blocks 2021-09-05 10:26:01 -05:00			`/build_sysroot/sysroot_src`
Initial commit 2020-05-10 09:54:30 -05:00			`/build_sysroot/Cargo.lock`
			`/build_sysroot/test_target/Cargo.lock`
			`/rust`
Implement basic inline asm support (#72) * Implement basic support for inline assembly * Disable LTO We don't support it yet at all * Handle `inout(reg) var` correctly Turns out that `+` readwrite output registers cannot be tied with input variables. * Add limited support for llvm_asm! * Handle CHANNEL correctly * Add support for arbitrary explicit registers * Handle symbols properly * Add rudimentary asm tests * Exclude llvm_asm! tests from tests runs * Insert `__builtin_unreachable()` after diverging asm blocks 2021-09-05 10:26:01 -05:00			`/simple-raytracer`
Initial commit 2020-05-10 09:54:30 -05:00			`/regex`
			`gimple*`
			`*asm`
			`res`
			`test-backend`
Update custom rustc instructions (#73) 2021-08-28 10:34:47 -05:00			`gcc_path`