rust/.gitignore

target
**/*.rs.bk
*.rlib
*.o
perf.data
perf.data.old
*.events
*.string*
/build_sysroot/sysroot
/build_sysroot/sysroot_src
/build_sysroot/Cargo.lock
/build_sysroot/test_target/Cargo.lock
/rust
/simple-raytracer
/regex
/rand
gimple*
*asm
res
test-backend
gcc_path
benchmarks
tools/llvm-project
tools/llvmint
tools/llvmint-2
# The `llvm` folder is generated by the `tools/generate_intrinsics.py` script to update intrinsics.
llvm
Initial commit 2020-05-10 09:54:30 -05:00			`target`
			`*/.rs.bk`
			`*.rlib`
			`*.o`
			`perf.data`
			`perf.data.old`
			`*.events`
			`.string`
			`/build_sysroot/sysroot`
Implement basic inline asm support (#72) * Implement basic support for inline assembly * Disable LTO We don't support it yet at all * Handle `inout(reg) var` correctly Turns out that `+` readwrite output registers cannot be tied with input variables. * Add limited support for llvm_asm! * Handle CHANNEL correctly * Add support for arbitrary explicit registers * Handle symbols properly * Add rudimentary asm tests * Exclude llvm_asm! tests from tests runs * Insert `__builtin_unreachable()` after diverging asm blocks 2021-09-05 10:26:01 -05:00			`/build_sysroot/sysroot_src`
Initial commit 2020-05-10 09:54:30 -05:00			`/build_sysroot/Cargo.lock`
			`/build_sysroot/test_target/Cargo.lock`
			`/rust`
Implement basic inline asm support (#72) * Implement basic support for inline assembly * Disable LTO We don't support it yet at all * Handle `inout(reg) var` correctly Turns out that `+` readwrite output registers cannot be tied with input variables. * Add limited support for llvm_asm! * Handle CHANNEL correctly * Add support for arbitrary explicit registers * Handle symbols properly * Add rudimentary asm tests * Exclude llvm_asm! tests from tests runs * Insert `__builtin_unreachable()` after diverging asm blocks 2021-09-05 10:26:01 -05:00			`/simple-raytracer`
Initial commit 2020-05-10 09:54:30 -05:00			`/regex`
Merge commit 'e8dca3e87d164d2806098c462c6ce41301341f68' into sync_from_cg_gcc 2022-06-06 21:04:37 -05:00			`/rand`
Initial commit 2020-05-10 09:54:30 -05:00			`gimple*`
			`*asm`
			`res`
			`test-backend`
Update custom rustc instructions (#73) 2021-08-28 10:34:47 -05:00			`gcc_path`
Merge commit '39683d8eb7a32a74bea96ecbf1e87675d3338506' into sync_cg_gcc-2022-03-26 2022-03-26 12:29:37 -05:00			`benchmarks`
Merge commit 'e8dca3e87d164d2806098c462c6ce41301341f68' into sync_from_cg_gcc 2022-06-06 21:04:37 -05:00			`tools/llvm-project`
			`tools/llvmint`
			`tools/llvmint-2`
Merge commit '1bbee3e217d75e7bc3bfe5d8c1b35e776fce96e6' into sync-cg_gcc-2023-06-19 2023-06-19 17:51:02 -05:00			# The `llvm` folder is generated by the `tools/generate_intrinsics.py` script to update intrinsics.
			`llvm`