2021-02-04 18:00:00 -06:00
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- // MIR for `t32` before Inline
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+ // MIR for `t32` after Inline
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fn t32() -> () {
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2023-06-06 08:47:00 -05:00
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let mut _0: ();
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let _1: ();
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let _2: ();
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let _3: ();
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let _4: ();
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+ scope 1 (inlined instruction_set_t32) {
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2022-11-07 13:07:07 -06:00
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+ }
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2023-06-06 08:47:00 -05:00
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+ scope 2 (inlined instruction_set_default) {
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2021-02-04 18:00:00 -06:00
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+ }
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bb0: {
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2023-06-06 08:47:00 -05:00
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StorageLive(_1);
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_1 = instruction_set_a32() -> [return: bb1, unwind unreachable];
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2021-02-04 18:00:00 -06:00
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}
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bb1: {
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2023-06-06 08:47:00 -05:00
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StorageDead(_1);
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StorageLive(_2);
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- _2 = instruction_set_t32() -> [return: bb2, unwind unreachable];
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2021-02-04 18:00:00 -06:00
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- }
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-
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- bb2: {
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2023-06-06 08:47:00 -05:00
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StorageDead(_2);
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StorageLive(_3);
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- _3 = instruction_set_default() -> [return: bb3, unwind unreachable];
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2022-11-07 13:07:07 -06:00
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- }
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-
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- bb3: {
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2023-06-06 08:47:00 -05:00
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StorageDead(_3);
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StorageLive(_4);
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- _4 = inline_always_and_using_inline_asm() -> [return: bb4, unwind unreachable];
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+ _4 = inline_always_and_using_inline_asm() -> [return: bb2, unwind unreachable];
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2021-02-04 18:00:00 -06:00
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}
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2022-11-07 13:07:07 -06:00
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- bb4: {
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2021-02-04 18:00:00 -06:00
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+ bb2: {
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2023-06-06 08:47:00 -05:00
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StorageDead(_4);
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_0 = const ();
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return;
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2021-02-04 18:00:00 -06:00
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}
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}
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