2023-04-23 04:38:37 -05:00
|
|
|
// MIR for `inclusive_loop` after PreCodegen
|
|
|
|
|
|
|
|
fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () {
|
|
|
|
debug start => _1; // in scope 0 at $DIR/range_iter.rs:+0:23: +0:28
|
|
|
|
debug end => _2; // in scope 0 at $DIR/range_iter.rs:+0:35: +0:38
|
|
|
|
debug f => _3; // in scope 0 at $DIR/range_iter.rs:+0:45: +0:46
|
|
|
|
let mut _0: (); // return place in scope 0 at $DIR/range_iter.rs:+0:62: +0:62
|
|
|
|
let mut _4: std::ops::RangeInclusive<u32>; // in scope 0 at $DIR/range_iter.rs:+1:14: +1:25
|
|
|
|
let mut _5: std::ops::RangeInclusive<u32>; // in scope 0 at $DIR/range_iter.rs:+1:14: +1:25
|
2023-05-21 13:44:37 -05:00
|
|
|
let mut _6: &mut std::ops::RangeInclusive<u32>; // in scope 0 at $DIR/range_iter.rs:+1:14: +1:25
|
2023-04-23 04:38:37 -05:00
|
|
|
let mut _7: std::option::Option<u32>; // in scope 0 at $DIR/range_iter.rs:+1:14: +1:25
|
2023-05-21 13:44:37 -05:00
|
|
|
let mut _8: isize; // in scope 0 at $DIR/range_iter.rs:+1:5: +3:6
|
|
|
|
let mut _10: &impl Fn(u32); // in scope 0 at $DIR/range_iter.rs:+2:9: +2:10
|
|
|
|
let mut _11: (u32,); // in scope 0 at $DIR/range_iter.rs:+2:9: +2:13
|
|
|
|
let _12: (); // in scope 0 at $DIR/range_iter.rs:+1:14: +1:25
|
2023-04-23 04:38:37 -05:00
|
|
|
scope 1 {
|
|
|
|
debug iter => _5; // in scope 1 at $DIR/range_iter.rs:+1:14: +1:25
|
2023-05-21 13:44:37 -05:00
|
|
|
let _9: u32; // in scope 1 at $DIR/range_iter.rs:+1:9: +1:10
|
2023-04-23 04:38:37 -05:00
|
|
|
scope 2 {
|
2023-05-21 13:44:37 -05:00
|
|
|
debug x => _9; // in scope 2 at $DIR/range_iter.rs:+1:9: +1:10
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
2023-06-08 02:34:53 -05:00
|
|
|
scope 5 (inlined iter::range::<impl Iterator for RangeInclusive<u32>>::next) { // at $DIR/range_iter.rs:29:14: 29:25
|
2023-05-21 13:44:37 -05:00
|
|
|
debug self => _6; // in scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
}
|
2023-06-08 02:34:53 -05:00
|
|
|
scope 3 (inlined RangeInclusive::<u32>::new) { // at $DIR/range_iter.rs:29:14: 29:25
|
2023-04-23 04:38:37 -05:00
|
|
|
debug start => _1; // in scope 3 at $SRC_DIR/core/src/ops/range.rs:LL:COL
|
|
|
|
debug end => _2; // in scope 3 at $SRC_DIR/core/src/ops/range.rs:LL:COL
|
|
|
|
}
|
2023-06-08 02:34:53 -05:00
|
|
|
scope 4 (inlined <RangeInclusive<u32> as IntoIterator>::into_iter) { // at $DIR/range_iter.rs:29:14: 29:25
|
2023-04-23 04:38:37 -05:00
|
|
|
debug self => _4; // in scope 4 at $SRC_DIR/core/src/iter/traits/collect.rs:LL:COL
|
|
|
|
}
|
|
|
|
|
|
|
|
bb0: {
|
|
|
|
_4 = RangeInclusive::<u32> { start: _1, end: _2, exhausted: const false }; // scope 3 at $SRC_DIR/core/src/ops/range.rs:LL:COL
|
|
|
|
StorageLive(_5); // scope 0 at $DIR/range_iter.rs:+1:14: +1:25
|
|
|
|
_5 = move _4; // scope 0 at $DIR/range_iter.rs:+1:14: +1:25
|
|
|
|
goto -> bb1; // scope 1 at $DIR/range_iter.rs:+1:5: +3:6
|
|
|
|
}
|
|
|
|
|
|
|
|
bb1: {
|
|
|
|
StorageLive(_7); // scope 1 at $DIR/range_iter.rs:+1:14: +1:25
|
2023-05-21 13:44:37 -05:00
|
|
|
_6 = &mut _5; // scope 1 at $DIR/range_iter.rs:+1:14: +1:25
|
|
|
|
_7 = <RangeInclusive<u32> as iter::range::RangeInclusiveIteratorImpl>::spec_next(_6) -> [return: bb2, unwind: bb8]; // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
|
2023-04-23 04:38:37 -05:00
|
|
|
// mir::Constant
|
|
|
|
// + span: $SRC_DIR/core/src/iter/range.rs:LL:COL
|
|
|
|
// + literal: Const { ty: for<'a> fn(&'a mut RangeInclusive<u32>) -> Option<<RangeInclusive<u32> as iter::range::RangeInclusiveIteratorImpl>::Item> {<RangeInclusive<u32> as iter::range::RangeInclusiveIteratorImpl>::spec_next}, val: Value(<ZST>) }
|
|
|
|
}
|
|
|
|
|
|
|
|
bb2: {
|
2023-05-21 13:44:37 -05:00
|
|
|
_8 = discriminant(_7); // scope 1 at $DIR/range_iter.rs:+1:14: +1:25
|
|
|
|
switchInt(move _8) -> [0: bb3, 1: bb5, otherwise: bb7]; // scope 1 at $DIR/range_iter.rs:+1:14: +1:25
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
bb3: {
|
2023-05-21 13:44:37 -05:00
|
|
|
StorageDead(_7); // scope 1 at $DIR/range_iter.rs:+3:5: +3:6
|
|
|
|
StorageDead(_5); // scope 0 at $DIR/range_iter.rs:+3:5: +3:6
|
|
|
|
drop(_3) -> bb4; // scope 0 at $DIR/range_iter.rs:+4:1: +4:2
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
bb4: {
|
2023-05-21 13:44:37 -05:00
|
|
|
return; // scope 0 at $DIR/range_iter.rs:+4:2: +4:2
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
bb5: {
|
2023-05-21 13:44:37 -05:00
|
|
|
_9 = ((_7 as Some).0: u32); // scope 1 at $DIR/range_iter.rs:+1:9: +1:10
|
|
|
|
StorageLive(_10); // scope 2 at $DIR/range_iter.rs:+2:9: +2:10
|
|
|
|
_10 = &_3; // scope 2 at $DIR/range_iter.rs:+2:9: +2:10
|
|
|
|
StorageLive(_11); // scope 2 at $DIR/range_iter.rs:+2:9: +2:13
|
|
|
|
_11 = (_9,); // scope 2 at $DIR/range_iter.rs:+2:9: +2:13
|
|
|
|
_12 = <impl Fn(u32) as Fn<(u32,)>>::call(move _10, move _11) -> [return: bb6, unwind: bb8]; // scope 2 at $DIR/range_iter.rs:+2:9: +2:13
|
|
|
|
// mir::Constant
|
2023-06-08 02:34:53 -05:00
|
|
|
// + span: $DIR/range_iter.rs:30:9: 30:10
|
2023-05-21 13:44:37 -05:00
|
|
|
// + literal: Const { ty: for<'a> extern "rust-call" fn(&'a impl Fn(u32), (u32,)) -> <impl Fn(u32) as FnOnce<(u32,)>>::Output {<impl Fn(u32) as Fn<(u32,)>>::call}, val: Value(<ZST>) }
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
bb6: {
|
2023-05-21 13:44:37 -05:00
|
|
|
StorageDead(_11); // scope 2 at $DIR/range_iter.rs:+2:12: +2:13
|
|
|
|
StorageDead(_10); // scope 2 at $DIR/range_iter.rs:+2:12: +2:13
|
|
|
|
StorageDead(_7); // scope 1 at $DIR/range_iter.rs:+3:5: +3:6
|
|
|
|
goto -> bb1; // scope 1 at $DIR/range_iter.rs:+1:5: +3:6
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
|
2023-05-21 13:44:37 -05:00
|
|
|
bb7: {
|
|
|
|
unreachable; // scope 1 at $DIR/range_iter.rs:+1:14: +1:25
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
bb8 (cleanup): {
|
2023-05-21 13:44:37 -05:00
|
|
|
drop(_3) -> [return: bb9, unwind terminate]; // scope 0 at $DIR/range_iter.rs:+4:1: +4:2
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
|
2023-05-21 13:44:37 -05:00
|
|
|
bb9 (cleanup): {
|
|
|
|
resume; // scope 0 at $DIR/range_iter.rs:+0:1: +4:2
|
2023-04-23 04:38:37 -05:00
|
|
|
}
|
|
|
|
}
|