2023-02-24 15:33:22 -06:00
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// MIR for `unchecked_shl_unsigned_smaller` after PreCodegen
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fn unchecked_shl_unsigned_smaller(_1: u16, _2: u32) -> u16 {
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2023-06-06 08:47:00 -05:00
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debug a => _1;
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debug b => _2;
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let mut _0: u16;
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2023-06-16 17:21:34 -05:00
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scope 1 (inlined core::num::<impl u16>::unchecked_shl) {
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debug self => _1;
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debug rhs => _2;
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let mut _3: u32;
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let mut _4: bool;
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let mut _5: u16;
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scope 2 {
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}
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}
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2023-02-24 15:33:22 -06:00
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bb0: {
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2023-06-16 17:21:34 -05:00
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StorageLive(_5);
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StorageLive(_4);
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StorageLive(_3);
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_3 = const 65535_u32;
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_4 = Le(_2, move _3);
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StorageDead(_3);
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assume(move _4);
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StorageDead(_4);
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_5 = _2 as u16 (IntToInt);
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2023-06-03 02:41:50 -05:00
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_0 = ShlUnchecked(_1, move _5);
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2023-06-16 17:21:34 -05:00
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StorageDead(_5);
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2023-06-06 08:47:00 -05:00
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return;
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2023-05-14 06:25:47 -05:00
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}
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2023-02-24 15:33:22 -06:00
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}
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