633 lines
30 KiB
Rust
633 lines
30 KiB
Rust
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use gccjit::{RValue, ToRValue, Type};
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use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
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use rustc_codegen_ssa::mir::operand::OperandValue;
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use rustc_codegen_ssa::mir::place::PlaceRef;
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use rustc_codegen_ssa::traits::{AsmBuilderMethods, AsmMethods, BaseTypeMethods, BuilderMethods, GlobalAsmOperandRef, InlineAsmOperandRef};
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use rustc_data_structures::fx::FxHashMap;
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use rustc_hir::LlvmInlineAsmInner;
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use rustc_middle::bug;
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use rustc_span::Span;
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use rustc_target::asm::*;
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use crate::builder::Builder;
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use crate::context::CodegenCx;
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use crate::type_of::LayoutGccExt;
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impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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fn codegen_llvm_inline_asm(&mut self, _ia: &LlvmInlineAsmInner, _outputs: Vec<PlaceRef<'tcx, RValue<'gcc>>>, mut _inputs: Vec<RValue<'gcc>>, _span: Span) -> bool {
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// TODO
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return true;
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/*let mut ext_constraints = vec![];
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let mut output_types = vec![];
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// Prepare the output operands
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let mut indirect_outputs = vec![];
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for (i, (out, &place)) in ia.outputs.iter().zip(&outputs).enumerate() {
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if out.is_rw {
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let operand = self.load_operand(place);
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if let OperandValue::Immediate(_) = operand.val {
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inputs.push(operand.immediate());
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}
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ext_constraints.push(i.to_string());
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}
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if out.is_indirect {
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let operand = self.load_operand(place);
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if let OperandValue::Immediate(_) = operand.val {
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indirect_outputs.push(operand.immediate());
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}
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} else {
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output_types.push(place.layout.gcc_type(self.cx()));
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}
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}
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if !indirect_outputs.is_empty() {
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indirect_outputs.extend_from_slice(&inputs);
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inputs = indirect_outputs;
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}
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let clobbers = ia.clobbers.iter().map(|s| format!("~{{{}}}", &s));
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// Default per-arch clobbers
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// Basically what clang does
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let arch_clobbers = match &self.sess().target.target.arch[..] {
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"x86" | "x86_64" => vec!["~{dirflag}", "~{fpsr}", "~{flags}"],
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"mips" | "mips64" => vec!["~{$1}"],
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_ => Vec::new(),
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};
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let all_constraints = ia
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.outputs
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.iter()
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.map(|out| out.constraint.to_string())
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.chain(ia.inputs.iter().map(|s| s.to_string()))
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.chain(ext_constraints)
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.chain(clobbers)
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.chain(arch_clobbers.iter().map(|s| (*s).to_string()))
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.collect::<Vec<String>>()
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.join(",");
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debug!("Asm Constraints: {}", &all_constraints);
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// Depending on how many outputs we have, the return type is different
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let num_outputs = output_types.len();
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let output_type = match num_outputs {
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0 => self.type_void(),
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1 => output_types[0],
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_ => self.type_struct(&output_types, false),
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};
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let asm = ia.asm.as_str();
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let r = inline_asm_call(
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self,
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&asm,
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&all_constraints,
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&inputs,
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output_type,
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ia.volatile,
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ia.alignstack,
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ia.dialect,
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);
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if r.is_none() {
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return false;
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}
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let r = r.unwrap();
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// Again, based on how many outputs we have
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let outputs = ia.outputs.iter().zip(&outputs).filter(|&(ref o, _)| !o.is_indirect);
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for (i, (_, &place)) in outputs.enumerate() {
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let v = if num_outputs == 1 { r } else { self.extract_value(r, i as u64) };
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OperandValue::Immediate(v).store(self, place);
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}
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// Store mark in a metadata node so we can map LLVM errors
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// back to source locations. See #17552.
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unsafe {
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let key = "srcloc";
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let kind = llvm::LLVMGetMDKindIDInContext(
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self.llcx,
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key.as_ptr() as *const c_char,
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key.len() as c_uint,
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);
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let val: &'ll Value = self.const_i32(span.ctxt().outer_expn().as_u32() as i32);
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llvm::LLVMSetMetadata(r, kind, llvm::LLVMMDNodeInContext(self.llcx, &val, 1));
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}
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true*/
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}
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fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], operands: &[InlineAsmOperandRef<'tcx, Self>], options: InlineAsmOptions, _span: &[Span]) {
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let asm_arch = self.tcx.sess.asm_arch.unwrap();
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let intel_dialect =
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match asm_arch {
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InlineAsmArch::X86 | InlineAsmArch::X86_64 if !options.contains(InlineAsmOptions::ATT_SYNTAX) => true,
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_ => false,
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};
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// Collect the types of output operands
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// FIXME: we do this here instead of later because of a bug in libgccjit where creating the
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// variable after the extended asm expression causes a segfault:
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// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100380
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let mut output_vars = FxHashMap::default();
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let mut operand_numbers = FxHashMap::default();
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let mut current_number = 0;
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for (idx, op) in operands.iter().enumerate() {
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match *op {
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InlineAsmOperandRef::Out { place, .. } => {
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let ty =
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match place {
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Some(place) => place.layout.gcc_type(self.cx, false),
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None => {
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// If the output is discarded, we don't really care what
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// type is used. We're just using this to tell GCC to
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// reserve the register.
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//dummy_output_type(self.cx, reg.reg_class())
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// NOTE: if no output value, we should not create one (it will be a
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// clobber).
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continue;
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},
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};
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let var = self.current_func().new_local(None, ty, "output_register");
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operand_numbers.insert(idx, current_number);
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current_number += 1;
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output_vars.insert(idx, var);
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}
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InlineAsmOperandRef::InOut { out_place, .. } => {
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let ty =
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match out_place {
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Some(place) => place.layout.gcc_type(self.cx, false),
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None => {
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// If the output is discarded, we don't really care what
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// type is used. We're just using this to tell GCC to
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// reserve the register.
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//dummy_output_type(self.cx, reg.reg_class())
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// NOTE: if no output value, we should not create one.
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continue;
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},
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};
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operand_numbers.insert(idx, current_number);
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current_number += 1;
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let var = self.current_func().new_local(None, ty, "output_register");
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output_vars.insert(idx, var);
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}
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_ => {}
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}
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}
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// All output operands must come before the input operands, hence the 2 loops.
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for (idx, op) in operands.iter().enumerate() {
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match *op {
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InlineAsmOperandRef::In { .. } | InlineAsmOperandRef::InOut { .. } => {
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operand_numbers.insert(idx, current_number);
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current_number += 1;
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},
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_ => (),
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}
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}
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// Build the template string
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let mut template_str = String::new();
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for piece in template {
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match *piece {
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InlineAsmTemplatePiece::String(ref string) => {
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if string.contains('%') {
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for c in string.chars() {
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if c == '%' {
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template_str.push_str("%%");
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}
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else {
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template_str.push(c);
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}
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}
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}
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else {
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template_str.push_str(string)
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}
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}
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InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
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match operands[operand_idx] {
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InlineAsmOperandRef::Out { reg, place: Some(_), .. } => {
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let modifier = modifier_to_gcc(asm_arch, reg.reg_class(), modifier);
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if let Some(modifier) = modifier {
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template_str.push_str(&format!("%{}{}", modifier, operand_numbers[&operand_idx]));
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} else {
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template_str.push_str(&format!("%{}", operand_numbers[&operand_idx]));
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}
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},
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InlineAsmOperandRef::Out { place: None, .. } => {
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unimplemented!("Out None");
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},
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InlineAsmOperandRef::In { reg, .. }
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| InlineAsmOperandRef::InOut { reg, .. } => {
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let modifier = modifier_to_gcc(asm_arch, reg.reg_class(), modifier);
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if let Some(modifier) = modifier {
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template_str.push_str(&format!("%{}{}", modifier, operand_numbers[&operand_idx]));
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} else {
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template_str.push_str(&format!("%{}", operand_numbers[&operand_idx]));
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}
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}
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InlineAsmOperandRef::Const { ref string } => {
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// Const operands get injected directly into the template
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template_str.push_str(string);
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}
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InlineAsmOperandRef::SymFn { .. }
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| InlineAsmOperandRef::SymStatic { .. } => {
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unimplemented!();
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// Only emit the raw symbol name
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//template_str.push_str(&format!("${{{}:c}}", op_idx[&operand_idx]));
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}
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}
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}
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}
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}
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let block = self.llbb();
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let template_str =
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if intel_dialect {
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template_str
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}
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else {
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// FIXME: this might break the "m" memory constraint:
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// https://stackoverflow.com/a/9347957/389119
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// TODO: only set on x86 platforms.
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format!(".att_syntax noprefix\n\t{}\n\t.intel_syntax noprefix", template_str)
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};
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let extended_asm = block.add_extended_asm(None, &template_str);
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// Collect the types of output operands
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let mut output_types = vec![];
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for (idx, op) in operands.iter().enumerate() {
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match *op {
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InlineAsmOperandRef::Out { reg, late, place } => {
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let ty =
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match place {
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Some(place) => place.layout.gcc_type(self.cx, false),
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None => {
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// If the output is discarded, we don't really care what
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// type is used. We're just using this to tell GCC to
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// reserve the register.
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dummy_output_type(self.cx, reg.reg_class())
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},
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};
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output_types.push(ty);
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//op_idx.insert(idx, constraints.len());
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let prefix = if late { "=" } else { "=&" };
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let constraint = format!("{}{}", prefix, reg_to_gcc(reg));
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if place.is_some() {
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let var = output_vars[&idx];
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extended_asm.add_output_operand(None, &constraint, var);
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}
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else {
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// NOTE: reg.to_string() returns the register name with quotes around it so
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// remove them.
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extended_asm.add_clobber(reg.to_string().trim_matches('"'));
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}
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}
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InlineAsmOperandRef::InOut { reg, late, in_value, out_place } => {
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let ty =
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match out_place {
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Some(out_place) => out_place.layout.gcc_type(self.cx, false),
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None => dummy_output_type(self.cx, reg.reg_class())
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};
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output_types.push(ty);
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//op_idx.insert(idx, constraints.len());
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// TODO: prefix of "+" for reading and writing?
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let prefix = if late { "=" } else { "=&" };
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let constraint = format!("{}{}", prefix, reg_to_gcc(reg));
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if out_place.is_some() {
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let var = output_vars[&idx];
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// TODO: also specify an output operand when out_place is none: that would
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// be the clobber but clobbers do not support general constraint like reg;
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// they only support named registers.
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// Not sure how we can do this. And the LLVM backend does not seem to add a
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// clobber.
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extended_asm.add_output_operand(None, &constraint, var);
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}
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let constraint = reg_to_gcc(reg);
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extended_asm.add_input_operand(None, &constraint, in_value.immediate());
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}
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InlineAsmOperandRef::In { reg, value } => {
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let constraint = reg_to_gcc(reg);
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extended_asm.add_input_operand(None, &constraint, value.immediate());
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}
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_ => {}
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}
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}
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/*if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) {
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match asm_arch {
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InlineAsmArch::AArch64 | InlineAsmArch::Arm => {
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constraints.push("~{cc}".to_string());
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}
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
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constraints.extend_from_slice(&[
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"~{dirflag}".to_string(),
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"~{fpsr}".to_string(),
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"~{flags}".to_string(),
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]);
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
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}
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}
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if !options.contains(InlineAsmOptions::NOMEM) {
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// This is actually ignored by LLVM, but it's probably best to keep
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// it just in case. LLVM instead uses the ReadOnly/ReadNone
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// attributes on the call instruction to optimize.
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constraints.push("~{memory}".to_string());
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}
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let volatile = !options.contains(InlineAsmOptions::PURE);
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let alignstack = !options.contains(InlineAsmOptions::NOSTACK);
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let output_type = match &output_types[..] {
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|
|
[] => self.type_void(),
|
||
|
|
[ty] => ty,
|
||
|
|
tys => self.type_struct(&tys, false),
|
||
|
|
};*/
|
||
|
|
|
||
|
|
/*let result = inline_asm_call(
|
||
|
|
self,
|
||
|
|
&template_str,
|
||
|
|
&constraints.join(","),
|
||
|
|
&inputs,
|
||
|
|
output_type,
|
||
|
|
volatile,
|
||
|
|
alignstack,
|
||
|
|
dialect,
|
||
|
|
span,
|
||
|
|
)
|
||
|
|
.unwrap_or_else(|| span_bug!(span, "LLVM asm constraint validation failed"));
|
||
|
|
|
||
|
|
if options.contains(InlineAsmOptions::PURE) {
|
||
|
|
if options.contains(InlineAsmOptions::NOMEM) {
|
||
|
|
llvm::Attribute::ReadNone.apply_callsite(llvm::AttributePlace::Function, result);
|
||
|
|
} else if options.contains(InlineAsmOptions::READONLY) {
|
||
|
|
llvm::Attribute::ReadOnly.apply_callsite(llvm::AttributePlace::Function, result);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
if options.contains(InlineAsmOptions::NOMEM) {
|
||
|
|
llvm::Attribute::InaccessibleMemOnly
|
||
|
|
.apply_callsite(llvm::AttributePlace::Function, result);
|
||
|
|
} else {
|
||
|
|
// LLVM doesn't have an attribute to represent ReadOnly + SideEffect
|
||
|
|
}
|
||
|
|
}*/
|
||
|
|
|
||
|
|
// Write results to outputs
|
||
|
|
for (idx, op) in operands.iter().enumerate() {
|
||
|
|
if let InlineAsmOperandRef::Out { place: Some(place), .. }
|
||
|
|
| InlineAsmOperandRef::InOut { out_place: Some(place), .. } = *op
|
||
|
|
{
|
||
|
|
OperandValue::Immediate(output_vars[&idx].to_rvalue()).store(self, place);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Converts a register class to a GCC constraint code.
|
||
|
|
// TODO: return &'static str instead?
|
||
|
|
fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> String {
|
||
|
|
match reg {
|
||
|
|
// For vector registers LLVM wants the register name to match the type size.
|
||
|
|
InlineAsmRegOrRegClass::Reg(reg) => {
|
||
|
|
// TODO: add support for vector register.
|
||
|
|
let constraint =
|
||
|
|
match reg.name() {
|
||
|
|
"ax" => "a",
|
||
|
|
"bx" => "b",
|
||
|
|
"cx" => "c",
|
||
|
|
"dx" => "d",
|
||
|
|
"si" => "S",
|
||
|
|
"di" => "D",
|
||
|
|
// TODO: for registers like r11, we have to create a register variable: https://stackoverflow.com/a/31774784/389119
|
||
|
|
// TODO: in this case though, it's a clobber, so it should work as r11.
|
||
|
|
// Recent nightly supports clobber() syntax, so update to it. It does not seem
|
||
|
|
// like it's implemented yet.
|
||
|
|
name => name, // FIXME: probably wrong.
|
||
|
|
};
|
||
|
|
constraint.to_string()
|
||
|
|
},
|
||
|
|
InlineAsmRegOrRegClass::RegClass(reg) => match reg {
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Bpf(_) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::mmx_reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
|
||
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
|
||
|
|
bug!("GCC backend does not support SPIR-V")
|
||
|
|
}
|
||
|
|
InlineAsmRegClass::Err => unreachable!(),
|
||
|
|
}
|
||
|
|
.to_string(),
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Type to use for outputs that are discarded. It doesn't really matter what
|
||
|
|
/// the type is, as long as it is valid for the constraint code.
|
||
|
|
fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegClass) -> Type<'gcc> {
|
||
|
|
match reg {
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
|
||
|
|
| InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
|
||
|
|
unimplemented!()
|
||
|
|
}
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => cx.type_f64(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
|
||
|
|
unimplemented!()
|
||
|
|
}
|
||
|
|
InlineAsmRegClass::Bpf(_) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
|
||
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
|
||
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
|
||
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
|
||
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
|
||
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => cx.type_f32(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
|
||
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => cx.type_i8(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::mmx_reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
|
||
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
|
||
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
|
||
|
|
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
|
||
|
|
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
|
||
|
|
bug!("LLVM backend does not support SPIR-V")
|
||
|
|
},
|
||
|
|
InlineAsmRegClass::Err => unreachable!(),
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
impl<'gcc, 'tcx> AsmMethods for CodegenCx<'gcc, 'tcx> {
|
||
|
|
fn codegen_global_asm(&self, template: &[InlineAsmTemplatePiece], operands: &[GlobalAsmOperandRef], options: InlineAsmOptions, _line_spans: &[Span]) {
|
||
|
|
let asm_arch = self.tcx.sess.asm_arch.unwrap();
|
||
|
|
|
||
|
|
// Default to Intel syntax on x86
|
||
|
|
let intel_syntax = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64)
|
||
|
|
&& !options.contains(InlineAsmOptions::ATT_SYNTAX);
|
||
|
|
|
||
|
|
// Build the template string
|
||
|
|
let mut template_str = String::new();
|
||
|
|
for piece in template {
|
||
|
|
match *piece {
|
||
|
|
InlineAsmTemplatePiece::String(ref string) => {
|
||
|
|
for line in string.lines() {
|
||
|
|
// NOTE: gcc does not allow inline comment, so remove them.
|
||
|
|
let line =
|
||
|
|
if let Some(index) = line.rfind("//") {
|
||
|
|
&line[..index]
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
line
|
||
|
|
};
|
||
|
|
template_str.push_str(line);
|
||
|
|
template_str.push('\n');
|
||
|
|
}
|
||
|
|
},
|
||
|
|
InlineAsmTemplatePiece::Placeholder { operand_idx, modifier: _, span: _ } => {
|
||
|
|
match operands[operand_idx] {
|
||
|
|
GlobalAsmOperandRef::Const { ref string } => {
|
||
|
|
// Const operands get injected directly into the
|
||
|
|
// template. Note that we don't need to escape $
|
||
|
|
// here unlike normal inline assembly.
|
||
|
|
template_str.push_str(string);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
let template_str =
|
||
|
|
if intel_syntax {
|
||
|
|
format!("{}\n\t.intel_syntax noprefix", template_str)
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
format!(".att_syntax\n\t{}\n\t.intel_syntax noprefix", template_str)
|
||
|
|
};
|
||
|
|
// NOTE: seems like gcc will put the asm in the wrong section, so set it to .text manually.
|
||
|
|
let template_str = format!(".pushsection .text\n{}\n.popsection", template_str);
|
||
|
|
self.context.add_top_level_asm(None, &template_str);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option<char>) -> Option<char> {
|
||
|
|
match reg {
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => modifier,
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => modifier,
|
||
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
|
||
|
|
| InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
|
||
|
|
unimplemented!()
|
||
|
|
//if modifier == Some('v') { None } else { modifier }
|
||
|
|
}
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
|
||
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
|
||
|
|
unimplemented!()
|
||
|
|
/*if modifier.is_none() {
|
||
|
|
Some('q')
|
||
|
|
} else {
|
||
|
|
modifier
|
||
|
|
}*/
|
||
|
|
}
|
||
|
|
InlineAsmRegClass::Bpf(_) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Hexagon(_) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Mips(_) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Nvptx(_) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::PowerPC(_) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
|
||
|
|
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
|
||
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => match modifier {
|
||
|
|
None if arch == InlineAsmArch::X86_64 => Some('q'),
|
||
|
|
None => Some('k'),
|
||
|
|
Some('l') => Some('b'),
|
||
|
|
Some('h') => Some('h'),
|
||
|
|
Some('x') => Some('w'),
|
||
|
|
Some('e') => Some('k'),
|
||
|
|
Some('r') => Some('q'),
|
||
|
|
_ => unreachable!(),
|
||
|
|
},
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::mmx_reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
|
||
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
|
||
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => unimplemented!() /*match (reg, modifier) {
|
||
|
|
(X86InlineAsmRegClass::xmm_reg, None) => Some('x'),
|
||
|
|
(X86InlineAsmRegClass::ymm_reg, None) => Some('t'),
|
||
|
|
(X86InlineAsmRegClass::zmm_reg, None) => Some('g'),
|
||
|
|
(_, Some('x')) => Some('x'),
|
||
|
|
(_, Some('y')) => Some('t'),
|
||
|
|
(_, Some('z')) => Some('g'),
|
||
|
|
_ => unreachable!(),
|
||
|
|
}*/,
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => unimplemented!(),
|
||
|
|
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
|
||
|
|
bug!("LLVM backend does not support SPIR-V")
|
||
|
|
},
|
||
|
|
InlineAsmRegClass::Err => unreachable!(),
|
||
|
|
}
|
||
|
|
}
|