368 lines
17 KiB
Rust
368 lines
17 KiB
Rust
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//! x86 run-time feature detection is OS independent.
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#[cfg(target_arch = "x86")]
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use crate::arch::x86::*;
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#[cfg(target_arch = "x86_64")]
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use crate::arch::x86_64::*;
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use crate::mem;
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use crate::detect::{bit, cache, Feature};
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/// Performs run-time feature detection.
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#[inline]
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pub fn check_for(x: Feature) -> bool {
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cache::test(x as u32, detect_features)
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}
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/// Run-time feature detection on x86 works by using the CPUID instruction.
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///
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/// The [CPUID Wikipedia page][wiki_cpuid] contains
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/// all the information about which flags to set to query which values, and in
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/// which registers these are reported.
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///
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/// The definitive references are:
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/// - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
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/// Instruction Set Reference, A-Z][intel64_ref].
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/// - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
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/// System Instructions][amd64_ref].
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///
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/// [wiki_cpuid]: https://en.wikipedia.org/wiki/CPUID
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/// [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
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/// [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
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#[allow(clippy::similar_names)]
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fn detect_features() -> cache::Initializer {
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let mut value = cache::Initializer::default();
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// If the x86 CPU does not support the CPUID instruction then it is too
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// old to support any of the currently-detectable features.
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if !has_cpuid() {
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return value;
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}
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// Calling `__cpuid`/`__cpuid_count` from here on is safe because the CPU
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// has `cpuid` support.
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// 0. EAX = 0: Basic Information:
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// - EAX returns the "Highest Function Parameter", that is, the maximum
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// leaf value for subsequent calls of `cpuinfo` in range [0,
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// 0x8000_0000]. - The vendor ID is stored in 12 u8 ascii chars,
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// returned in EBX, EDX, and ECX (in that order):
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let (max_basic_leaf, vendor_id) = unsafe {
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let CpuidResult {
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eax: max_basic_leaf,
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ebx,
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ecx,
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edx,
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} = __cpuid(0);
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let vendor_id: [[u8; 4]; 3] = [
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mem::transmute(ebx),
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mem::transmute(edx),
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mem::transmute(ecx),
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];
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let vendor_id: [u8; 12] = mem::transmute(vendor_id);
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(max_basic_leaf, vendor_id)
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};
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if max_basic_leaf < 1 {
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// Earlier Intel 486, CPUID not implemented
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return value;
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}
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// EAX = 1, ECX = 0: Queries "Processor Info and Feature Bits";
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// Contains information about most x86 features.
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let CpuidResult {
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ecx: proc_info_ecx,
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edx: proc_info_edx,
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..
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} = unsafe { __cpuid(0x0000_0001_u32) };
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// EAX = 7, ECX = 0: Queries "Extended Features";
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// Contains information about bmi,bmi2, and avx2 support.
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let (extended_features_ebx, extended_features_ecx) = if max_basic_leaf >= 7 {
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let CpuidResult { ebx, ecx, .. } = unsafe { __cpuid(0x0000_0007_u32) };
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(ebx, ecx)
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} else {
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(0, 0) // CPUID does not support "Extended Features"
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};
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// EAX = 0x8000_0000, ECX = 0: Get Highest Extended Function Supported
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// - EAX returns the max leaf value for extended information, that is,
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// `cpuid` calls in range [0x8000_0000; u32::MAX]:
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let CpuidResult {
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eax: extended_max_basic_leaf,
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..
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} = unsafe { __cpuid(0x8000_0000_u32) };
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// EAX = 0x8000_0001, ECX=0: Queries "Extended Processor Info and Feature
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// Bits"
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let extended_proc_info_ecx = if extended_max_basic_leaf >= 1 {
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let CpuidResult { ecx, .. } = unsafe { __cpuid(0x8000_0001_u32) };
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ecx
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} else {
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0
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};
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{
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// borrows value till the end of this scope:
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let mut enable = |r, rb, f| {
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if bit::test(r as usize, rb) {
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value.set(f as u32);
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}
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};
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enable(proc_info_ecx, 0, Feature::sse3);
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enable(proc_info_ecx, 1, Feature::pclmulqdq);
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enable(proc_info_ecx, 9, Feature::ssse3);
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enable(proc_info_ecx, 13, Feature::cmpxchg16b);
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enable(proc_info_ecx, 19, Feature::sse4_1);
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enable(proc_info_ecx, 20, Feature::sse4_2);
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enable(proc_info_ecx, 23, Feature::popcnt);
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enable(proc_info_ecx, 25, Feature::aes);
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enable(proc_info_ecx, 29, Feature::f16c);
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enable(proc_info_ecx, 30, Feature::rdrand);
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enable(extended_features_ebx, 18, Feature::rdseed);
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enable(extended_features_ebx, 19, Feature::adx);
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enable(extended_features_ebx, 11, Feature::rtm);
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enable(proc_info_edx, 4, Feature::tsc);
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enable(proc_info_edx, 23, Feature::mmx);
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enable(proc_info_edx, 24, Feature::fxsr);
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enable(proc_info_edx, 25, Feature::sse);
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enable(proc_info_edx, 26, Feature::sse2);
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enable(extended_features_ebx, 29, Feature::sha);
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enable(extended_features_ebx, 3, Feature::bmi);
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enable(extended_features_ebx, 8, Feature::bmi2);
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// `XSAVE` and `AVX` support:
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let cpu_xsave = bit::test(proc_info_ecx as usize, 26);
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if cpu_xsave {
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// 0. Here the CPU supports `XSAVE`.
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// 1. Detect `OSXSAVE`, that is, whether the OS is AVX enabled and
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// supports saving the state of the AVX/AVX2 vector registers on
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// context-switches, see:
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//
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// - [intel: is avx enabled?][is_avx_enabled],
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// - [mozilla: sse.cpp][mozilla_sse_cpp].
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//
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// [is_avx_enabled]: https://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
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// [mozilla_sse_cpp]: https://hg.mozilla.org/mozilla-central/file/64bab5cbb9b6/mozglue/build/SSE.cpp#l190
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let cpu_osxsave = bit::test(proc_info_ecx as usize, 27);
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if cpu_osxsave {
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// 2. The OS must have signaled the CPU that it supports saving and
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// restoring the:
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//
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// * SSE -> `XCR0.SSE[1]`
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// * AVX -> `XCR0.AVX[2]`
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// * AVX-512 -> `XCR0.AVX-512[7:5]`.
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//
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// by setting the corresponding bits of `XCR0` to `1`.
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//
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// This is safe because the CPU supports `xsave`
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// and the OS has set `osxsave`.
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let xcr0 = unsafe { _xgetbv(0) };
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// Test `XCR0.SSE[1]` and `XCR0.AVX[2]` with the mask `0b110 == 6`:
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let os_avx_support = xcr0 & 6 == 6;
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// Test `XCR0.AVX-512[7:5]` with the mask `0b1110_0000 == 224`:
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let os_avx512_support = xcr0 & 224 == 224;
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// Only if the OS and the CPU support saving/restoring the AVX
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// registers we enable `xsave` support:
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if os_avx_support {
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// See "13.3 ENABLING THE XSAVE FEATURE SET AND XSAVE-ENABLED
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// FEATURES" in the "Intel® 64 and IA-32 Architectures Software
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// Developer’s Manual, Volume 1: Basic Architecture":
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//
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// "Software enables the XSAVE feature set by setting
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// CR4.OSXSAVE[bit 18] to 1 (e.g., with the MOV to CR4
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// instruction). If this bit is 0, execution of any of XGETBV,
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// XRSTOR, XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and XSETBV
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// causes an invalid-opcode exception (#UD)"
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//
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enable(proc_info_ecx, 26, Feature::xsave);
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// For `xsaveopt`, `xsavec`, and `xsaves` we need to query:
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// Processor Extended State Enumeration Sub-leaf (EAX = 0DH,
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// ECX = 1):
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if max_basic_leaf >= 0xd {
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let CpuidResult {
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eax: proc_extended_state1_eax,
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..
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} = unsafe { __cpuid_count(0xd_u32, 1) };
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enable(proc_extended_state1_eax, 0, Feature::xsaveopt);
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enable(proc_extended_state1_eax, 1, Feature::xsavec);
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enable(proc_extended_state1_eax, 3, Feature::xsaves);
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}
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// FMA (uses 256-bit wide registers):
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enable(proc_info_ecx, 12, Feature::fma);
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// And AVX/AVX2:
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enable(proc_info_ecx, 28, Feature::avx);
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enable(extended_features_ebx, 5, Feature::avx2);
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// For AVX-512 the OS also needs to support saving/restoring
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// the extended state, only then we enable AVX-512 support:
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if os_avx512_support {
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enable(extended_features_ebx, 16, Feature::avx512f);
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enable(extended_features_ebx, 17, Feature::avx512dq);
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enable(extended_features_ebx, 21, Feature::avx512_ifma);
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enable(extended_features_ebx, 26, Feature::avx512pf);
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enable(extended_features_ebx, 27, Feature::avx512er);
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enable(extended_features_ebx, 28, Feature::avx512cd);
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enable(extended_features_ebx, 30, Feature::avx512bw);
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enable(extended_features_ebx, 31, Feature::avx512vl);
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enable(extended_features_ecx, 1, Feature::avx512_vbmi);
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enable(extended_features_ecx, 14, Feature::avx512_vpopcntdq);
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}
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}
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}
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}
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// This detects ABM on AMD CPUs and LZCNT on Intel CPUs.
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// On intel CPUs with popcnt, lzcnt implements the
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// "missing part" of ABM, so we map both to the same
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// internal feature.
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//
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// The `is_x86_feature_detected!("lzcnt")` macro then
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// internally maps to Feature::abm.
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enable(extended_proc_info_ecx, 5, Feature::abm);
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// As Hygon Dhyana originates from AMD technology and shares most of the architecture with
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// AMD's family 17h, but with different CPU Vendor ID("HygonGenuine")/Family series
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// number(Family 18h).
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//
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// For CPUID feature bits, Hygon Dhyana(family 18h) share the same definition with AMD
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// family 17h.
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//
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// Related AMD CPUID specification is https://www.amd.com/system/files/TechDocs/25481.pdf.
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// Related Hygon kernel patch can be found on
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// http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
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if vendor_id == *b"AuthenticAMD" || vendor_id == *b"HygonGenuine" {
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// These features are available on AMD arch CPUs:
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enable(extended_proc_info_ecx, 6, Feature::sse4a);
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enable(extended_proc_info_ecx, 21, Feature::tbm);
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}
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}
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value
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}
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#[cfg(test)]
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mod tests {
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extern crate cupid;
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#[test]
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fn dump() {
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println!("aes: {:?}", is_x86_feature_detected!("aes"));
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println!("pclmulqdq: {:?}", is_x86_feature_detected!("pclmulqdq"));
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println!("rdrand: {:?}", is_x86_feature_detected!("rdrand"));
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println!("rdseed: {:?}", is_x86_feature_detected!("rdseed"));
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println!("tsc: {:?}", is_x86_feature_detected!("tsc"));
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println!("sse: {:?}", is_x86_feature_detected!("sse"));
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println!("sse2: {:?}", is_x86_feature_detected!("sse2"));
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println!("sse3: {:?}", is_x86_feature_detected!("sse3"));
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println!("ssse3: {:?}", is_x86_feature_detected!("ssse3"));
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println!("sse4.1: {:?}", is_x86_feature_detected!("sse4.1"));
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println!("sse4.2: {:?}", is_x86_feature_detected!("sse4.2"));
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println!("sse4a: {:?}", is_x86_feature_detected!("sse4a"));
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println!("sha: {:?}", is_x86_feature_detected!("sha"));
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println!("avx: {:?}", is_x86_feature_detected!("avx"));
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println!("avx2: {:?}", is_x86_feature_detected!("avx2"));
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println!("avx512f {:?}", is_x86_feature_detected!("avx512f"));
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println!("avx512cd {:?}", is_x86_feature_detected!("avx512cd"));
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println!("avx512er {:?}", is_x86_feature_detected!("avx512er"));
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println!("avx512pf {:?}", is_x86_feature_detected!("avx512pf"));
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println!("avx512bw {:?}", is_x86_feature_detected!("avx512bw"));
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println!("avx512dq {:?}", is_x86_feature_detected!("avx512dq"));
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println!("avx512vl {:?}", is_x86_feature_detected!("avx512vl"));
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println!("avx512_ifma {:?}", is_x86_feature_detected!("avx512ifma"));
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println!("avx512_vbmi {:?}", is_x86_feature_detected!("avx512vbmi"));
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println!(
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"avx512_vpopcntdq {:?}",
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is_x86_feature_detected!("avx512vpopcntdq")
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);
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println!("fma: {:?}", is_x86_feature_detected!("fma"));
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println!("abm: {:?}", is_x86_feature_detected!("abm"));
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println!("bmi: {:?}", is_x86_feature_detected!("bmi1"));
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println!("bmi2: {:?}", is_x86_feature_detected!("bmi2"));
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println!("tbm: {:?}", is_x86_feature_detected!("tbm"));
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println!("popcnt: {:?}", is_x86_feature_detected!("popcnt"));
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println!("lzcnt: {:?}", is_x86_feature_detected!("lzcnt"));
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println!("fxsr: {:?}", is_x86_feature_detected!("fxsr"));
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println!("xsave: {:?}", is_x86_feature_detected!("xsave"));
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|||
|
|
println!("xsaveopt: {:?}", is_x86_feature_detected!("xsaveopt"));
|
|||
|
|
println!("xsaves: {:?}", is_x86_feature_detected!("xsaves"));
|
|||
|
|
println!("xsavec: {:?}", is_x86_feature_detected!("xsavec"));
|
|||
|
|
println!("cmpxchg16b: {:?}", is_x86_feature_detected!("cmpxchg16b"));
|
|||
|
|
println!("adx: {:?}", is_x86_feature_detected!("adx"));
|
|||
|
|
println!("rtm: {:?}", is_x86_feature_detected!("rtm"));
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
#[test]
|
|||
|
|
fn compare_with_cupid() {
|
|||
|
|
let information = cupid::master().unwrap();
|
|||
|
|
assert_eq!(is_x86_feature_detected!("aes"), information.aesni());
|
|||
|
|
assert_eq!(
|
|||
|
|
is_x86_feature_detected!("pclmulqdq"),
|
|||
|
|
information.pclmulqdq()
|
|||
|
|
);
|
|||
|
|
assert_eq!(is_x86_feature_detected!("rdrand"), information.rdrand());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("rdseed"), information.rdseed());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("tsc"), information.tsc());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("sse"), information.sse());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("sse2"), information.sse2());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("sse3"), information.sse3());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("ssse3"), information.ssse3());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("sse4.1"), information.sse4_1());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("sse4.2"), information.sse4_2());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("sse4a"), information.sse4a());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("sha"), information.sha());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx"), information.avx());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx2"), information.avx2());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx512f"), information.avx512f());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx512cd"), information.avx512cd());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx512er"), information.avx512er());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx512pf"), information.avx512pf());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx512bw"), information.avx512bw());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx512dq"), information.avx512dq());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("avx512vl"), information.avx512vl());
|
|||
|
|
assert_eq!(
|
|||
|
|
is_x86_feature_detected!("avx512ifma"),
|
|||
|
|
information.avx512_ifma()
|
|||
|
|
);
|
|||
|
|
assert_eq!(
|
|||
|
|
is_x86_feature_detected!("avx512vbmi"),
|
|||
|
|
information.avx512_vbmi()
|
|||
|
|
);
|
|||
|
|
assert_eq!(
|
|||
|
|
is_x86_feature_detected!("avx512vpopcntdq"),
|
|||
|
|
information.avx512_vpopcntdq()
|
|||
|
|
);
|
|||
|
|
assert_eq!(is_x86_feature_detected!("fma"), information.fma());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("bmi1"), information.bmi1());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("bmi2"), information.bmi2());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("popcnt"), information.popcnt());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("abm"), information.lzcnt());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("tbm"), information.tbm());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("lzcnt"), information.lzcnt());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("xsave"), information.xsave());
|
|||
|
|
assert_eq!(is_x86_feature_detected!("xsaveopt"), information.xsaveopt());
|
|||
|
|
assert_eq!(
|
|||
|
|
is_x86_feature_detected!("xsavec"),
|
|||
|
|
information.xsavec_and_xrstor()
|
|||
|
|
);
|
|||
|
|
assert_eq!(
|
|||
|
|
is_x86_feature_detected!("xsaves"),
|
|||
|
|
information.xsaves_xrstors_and_ia32_xss()
|
|||
|
|
);
|
|||
|
|
assert_eq!(
|
|||
|
|
is_x86_feature_detected!("cmpxchg16b"),
|
|||
|
|
information.cmpxchg16b(),
|
|||
|
|
);
|
|||
|
|
assert_eq!(is_x86_feature_detected!("adx"), information.adx(),);
|
|||
|
|
assert_eq!(is_x86_feature_detected!("rtm"), information.rtm(),);
|
|||
|
|
}
|
|||
|
|
}
|